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From: cvs at opencores.org<cvs@o...>
Date: Wed Apr 19 12:19:59 CEST 2006
Subject: [cvs-checkins] MODIFIED: ofdm ...
Date: 00/06/04 19:12:19

Modified: ofdm/vhdl txrx.vhd
Log:
no message


Revision Changes Path
1.2 ofdm/vhdl/txrx.vhd

http://www.opencores.org/cvsweb.shtml/ofdm/vhdl/txrx.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: txrx.vhd
===================================================================
RCS file: /cvsroot/tmsiqueira/ofdm/vhdl/txrx.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- txrx.vhd 12 Apr 2006 02:49:30 -0000 1.1
+++ txrx.vhd 19 Apr 2006 10:19:59 -0000 1.2
@@ -3,11 +3,6 @@
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
entity txrx is
Port ( clk : in std_logic;
rst : in std_logic;
@@ -70,7 +65,6 @@
end if;
end process;

-
process(clk,rst)
begin
if rst = '1' then