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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 17 17:34:22 CEST 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/04 17:17:34 Added: jop/vhdl/scio sc_sigdel.vhd scio_mikjen.vhd
Log:
JOP version for Jens & Mikael (micro in/out on baseio)
Revision Changes Path
1.1 jop/vhdl/scio/sc_sigdel.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/sc_sigdel.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: sc_sigdel.vhd
===================================================================
--
-- sc_sigdel.vhd
--
-- A simple sigma-delta ADC and PWM DAC for the SimpCon interface
--
-- Author: Martin Schoeberl martin@j...
--
--
-- resources on Cyclone
--
-- xx LCs, max xx MHz
--
--
-- 2006-04-16 first version
--
-- todo:
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.jop_config.all;
entity sc_sigdel is
generic (addr_bits : integer; fsamp : integer);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon interface
address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
rdy_cnt : out unsigned(1 downto 0);
-- io ports
sdi : in std_logic; -- input of the sigma-delta ADC
sdo : out std_logic; -- output of the sigma-delta ADC
dac : out std_logic -- output of the PWM DAC
);
end sc_sigdel;
architecture rtl of sc_sigdel is
-- we use a 10MHz sigma-delta clock
-- constant SDTICK : integer := (clk_freq+5000000) / 10000000;
constant SDTICK : integer := 6;
signal clksd : integer range 0 to SDTICK;
-- constant CNT_MAX : integer := (SDTICK+fsamp/2) / fsamp;
constant CNT_MAX : integer := 10000000/20000;
signal cnt : integer range 0 to CNT_MAX;
signal rx_d : std_logic;
signal serdata : std_logic;
signal spike : std_logic_vector(2 downto 0); -- sync in, filter
signal sum : unsigned(15 downto 0);
signal delta : unsigned(15 downto 0);
signal audio_in : std_logic_vector(15 downto 0);
signal audio_out : std_logic_vector(15 downto 0);
signal sample_rdy : std_logic;
signal sample_rd : std_logic;
signal sample_wr : std_logic;
begin
rdy_cnt <= "00"; -- no wait states
-- we use only 16 bits
-- bit 31 is the ready bit
rd_data(30 downto 16) <= (others => '0');
--
-- The registered MUX is all we need for a SimpCon read.
-- The read data is stored in registered rd_data.
--
process(clk, reset)
begin
if (reset='1') then
rd_data(15 downto 0) <= (others => '0');
rd_data(31) <= '0';
sample_rd <= '0';
elsif rising_edge(clk) then
sample_rd <= '0';
if rd='1' then
rd_data(15 downto 0) <= audio_in;
rd_data(31) <= sample_rdy;
sample_rd <= '1';
end if;
end if;
end process;
--
-- SimpCon write is very simple
--
process(clk, reset)
begin
if (reset='1') then
audio_out <= (others => '0');
sample_wr <= '0';
elsif rising_edge(clk) then
sample_wr <= '0';
if wr='1' then
audio_out <= wr_data(15 downto 0);
sample_wr <= '1';
end if;
end if;
end process;
--
-- Here we go with the simple sigma-delta converter:
--
process(clk, reset)
begin
if reset='1' then
spike <= "000";
clksd <= 0;
cnt <= 0;
sum <= (others => '0');
sample_rdy <= '0';
elsif rising_edge(clk) then
if clksd=0 then
clksd <= SDTICK-1;
spike(0) <= sdi;
spike(2 downto 1) <= spike(1 downto 0);
sdo <= not rx_d;
serdata <= rx_d;
if cnt=0 then
cnt <= CNT_MAX-1;
audio_in <= std_logic_vector(sum);
sample_rdy <= '1';
sum <= (others => '0');
-- BTW: we miss one sigma-delta sample here...
else
cnt <= cnt-1;
if serdata='1' then
sum <= sum+1;
end if;
end if;
else
clksd <= clksd-1;
end if;
-- reset ready flag after read
if sample_rd='1' then
sample_rdy <= '0';
end if;
end if;
end process;
--
-- filter input (majority voting)
--
with spike select
rx_d <= '0' when "000",
'0' when "001",
'0' when "010",
'1' when "011",
'0' when "100",
'1' when "101",
'1' when "110",
'1' when "111",
'X' when others;
--
-- and here comes the primitive version of the
-- digital delta part - not really delta...
-- it's just a simple PWM...
--
process(clk, reset)
begin
if reset='1' then
delta <= (others => '0');
dac <= '0';
elsif rising_edge(clk) then
if clksd=0 then -- recycle sd tick
if cnt=0 then -- recycle the adc counter
-- delta <= unsigned(audio_out);
delta <= unsigned(audio_in);
else
dac <= '0';
if delta /= 0 then
delta <= delta-1;
dac <= '1';
end if;
end if;
end if;
end if;
end process;
end rtl;
1.1 jop/vhdl/scio/scio_mikjen.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/scio_mikjen.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: scio_mikjen.vhd
===================================================================
--
-- scio_mikjen.vhd
--
-- io devices for baseio print (TAL)
-- special version for Mikael and Jens
--
--
-- io address mapping:
--
-- IO Base is 0xffffff80 for 'fast' constants (bipush)
--
-- 0x00 0-3 system clock counter, us counter, timer int, wd bit
-- 0x10 0-1 uart (download)
--
-- 0x20 reserved for USB port -- System.out.print() writes to it!
-- TAL
-- 0x40 0 in pins, led outs
-- 0x40 1 out pins
-- 0x40 1 ADC1 input
-- 0x40 2 ADC2 input
-- 0x40 3 ADC3 input (battery watch)
-- 0x50 0 isa control and addr write
-- 0x50 1 isa data
--
-- status word in uarts:
-- 0 uart transmit data register empty
-- 1 uart read data register full
--
--
-- todo:
--
--
-- 2003-07-09 created
-- 2005-08-27 ignore ncts on uart
-- 2005-12-27 change for SimpCon, HW hand shake is programmable
-- for uart_tal
-- 2006-04-16 adapted for Jens & Mikael
--
--
--
-- IO devices specific for TAL
--
-- address:
-- 0 input pins and led output
-- 1 output pins
-- 1-3 ADC
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sc_tal is
generic (addr_bits : integer;
clk_freq : integer);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon interface
address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
rdy_cnt : out unsigned(1 downto 0);
-- io ports
i : in std_logic_vector(10 downto 1);
lo : out std_logic_vector(14 downto 1);
bat : out std_logic;
o : out std_logic_vector(4 downto 1);
sdi : in std_logic_vector(2 downto 0);
sdo : out std_logic_vector(2 downto 0)
);
end sc_tal;
architecture rtl of sc_tal is
signal inreg : std_logic_vector(10 downto 1);
signal led : std_logic_vector(14 downto 1);
type sd_dout_type is array(0 to 2) of std_logic_vector(15 downto 0);
signal sd_dout : sd_dout_type;
begin
rdy_cnt <= "00"; -- no wait states
gsd: for i in 0 to 2 generate
sd: entity work.sigdel
generic map (
clk_freq => clk_freq
)
port map (
clk => clk,
reset => reset,
dout => sd_dout(i),
sdi => sdi(i),
sdo => sdo(i)
);
end generate;
--
-- register inputs
--
process(clk, i)
begin
if rising_edge(clk) then
inreg <= not i; -- input is low active
end if;
end process;
process(clk, reset)
begin
if (reset='1') then
rd_data <= (others => '0');
elsif rising_edge(clk) then
if rd='1' then
case address(1 downto 0) is
when "00" =>
rd_data <= std_logic_vector(to_unsigned(0, 22)) & inreg;
when "01" =>
rd_data <= std_logic_vector(to_unsigned(0, 16)) & sd_dout(0);
when "10" =>
rd_data <= std_logic_vector(to_unsigned(0, 16)) & sd_dout(1);
when others =>
rd_data <= std_logic_vector(to_unsigned(0, 16)) & sd_dout(2);
end case;
end if;
end if;
end process;
process(clk, reset)
begin
if (reset='1') then
led <= (others => '0');
bat <= '1';
o <= (others => '0');
elsif rising_edge(clk) then
if wr='1' then
if address(0)='0' then
led <= wr_data(13 downto 0);
bat <= not wr_data(31);
else
o <= wr_data(3 downto 0);
end if;
end if;
end if;
end process;
--
-- low activ OC for LEDs
--
lo(1) <= '0' when led(1)='1' else 'Z';
lo(2) <= '0' when led(2)='1' else 'Z';
lo(3) <= '0' when led(3)='1' else 'Z';
lo(4) <= '0' when led(4)='1' else 'Z';
lo(5) <= '0' when led(5)='1' else 'Z';
lo(6) <= '0' when led(6)='1' else 'Z';
lo(7) <= '0' when led(7)='1' else 'Z';
lo(8) <= '0' when led(8)='1' else 'Z';
lo(9) <= '0' when led(9)='1' else 'Z';
lo(10) <= '0' when led(10)='1' else 'Z';
lo(11) <= '0' when led(11)='1' else 'Z';
lo(12) <= '0' when led(12)='1' else 'Z';
lo(13) <= '0' when led(13)='1' else 'Z';
lo(14) <= '0' when led(14)='1' else 'Z';
end rtl;
--
-- basio scio
--
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.jop_types.all;
use work.jop_config.all;
entity scio is
generic (addr_bits : integer);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon interface
address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
rdy_cnt : out unsigned(1 downto 0);
-- interrupt
irq : out std_logic;
irq_ena : out std_logic;
-- exception
exc_req : in exception_type;
exc_int : out std_logic;
-- serial interface
txd : out std_logic;
rxd : in std_logic;
ncts : in std_logic;
nrts : out std_logic;
-- watch dog
wd : out std_logic;
-- core i/o pins
l : inout std_logic_vector(20 downto 1);
r : inout std_logic_vector(20 downto 1);
t : inout std_logic_vector(6 downto 1);
b : inout std_logic_vector(10 downto 1)
);
end scio;
architecture rtl of scio is
constant SLAVE_CNT : integer := 7;
-- SLAVE_CNT <= 2**DECODE_BITS
constant DECODE_BITS : integer := 3;
-- number of bits that can be used inside the slave
constant SLAVE_ADDR_BITS : integer := 4;
type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;
signal sc_rd, sc_wr : slave_bit;
type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0);
signal sc_dout : slave_dout;
type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);
signal sc_rdy_cnt : slave_rdy_cnt;
signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1;
signal lo : std_logic_vector(14 downto 1);
signal bat : std_logic;
signal sdi : std_logic_vector(2 downto 0);
signal sdo : std_logic_vector(2 downto 0);
signal isa_a : std_logic_vector(4 downto 0);
signal mic_sdi, mic_sdo, audio_out : std_logic;
begin
--
-- unused and input pins tri state
--
r(2 downto 1) <= (others => 'Z');
r(20 downto 6) <= (others => 'Z');
assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";
sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
-- What happens when sel_reg > SLAVE_CNT-1??
rd_data <= sc_dout(sel_reg);
-- rdy_cnt <= sc_rdy_cnt(sel_reg);
rdy_cnt <= "00";
--
-- Connect SLAVE_CNT slaves
--
gsl: for i in 0 to SLAVE_CNT-1 generate
sc_rd(i) <= rd when i=sel else '0';
sc_wr(i) <= wr when i=sel else '0';
end generate;
--
-- Register read mux selector
--
process(clk, reset)
begin
if (reset='1') then
sel_reg <= 0;
elsif rising_edge(clk) then
if rd='1' then
sel_reg <= sel;
end if;
end if;
end process;
cmp_cnt: entity work.sc_cnt generic map (
addr_bits => SLAVE_ADDR_BITS,
clk_freq => clk_freq
)
port map(
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(0),
wr => sc_wr(0),
rd_data => sc_dout(0),
rdy_cnt => sc_rdy_cnt(0),
irq => irq,
irq_ena => irq_ena,
exc_req => exc_req,
exc_int => exc_int,
wd => wd
);
cmp_ua: entity work.sc_uart_tal generic map (
addr_bits => SLAVE_ADDR_BITS,
clk_freq => clk_freq,
baud_rate => 115200,
txf_depth => 4,
txf_thres => 2,
rxf_depth => 16,
rxf_thres => 8
)
port map(
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(1),
wr => sc_wr(1),
rd_data => sc_dout(1),
rdy_cnt => sc_rdy_cnt(1),
txd => txd,
rxd => rxd,
ncts => ncts,
nrts => nrts,
dtr => l(11)
);
-- b(1 to 10) <= lo(10 downto 1); Quartus does not compile!!!
-- Mikael & Jens:
-- change to the pins you are using!
-- be carful to NOT confuse the signals l and lo!
-- l(12) <= lo(14);
l(13) <= lo(13);
-- l(14) <= lo(12);
l(15) <= lo(11);
b(1) <= lo(10);
b(2) <= lo(9);
b(3) <= lo(8);
b(4) <= lo(7);
b(5) <= lo(6);
b(6) <= lo(5);
b(7) <= lo(4);
b(8) <= lo(3);
-- b(9) <= lo(2);
b(10) <= lo(1);
l(16) <= bat;
-- we use three of the LED pins for the micro sigdel
-- and the audio out:
mic_sdi <= l(12);
l(14) <= mic_sdo;
b(9) <= audio_out;
-- slave 2 is reserved for USB and System.out writes to it!!!
-- slave 3 is reserved for TAL simulation on the PC
--
-- TAL stuff (IO ports, sigdel converter)
--
cmp_tal: entity work.sc_tal generic map (
addr_bits => SLAVE_ADDR_BITS,
clk_freq => clk_freq
)
port map(
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(4),
wr => sc_wr(4),
rd_data => sc_dout(4),
rdy_cnt => sc_rdy_cnt(4),
i => r(20 downto 11), -- input pins
lo => lo, -- LEDs
bat => bat, -- battery on
o => l(20 downto 17), -- output pins
sdi => sdi,
sdo => sdo
);
-- ADC 1
sdi(0) <= r(7);
r(4) <= sdo(0);
-- ADC 2
sdi(1) <= r(6);
r(5) <= sdo(1);
-- ADC 3 (battery)
sdi(2) <= r(8);
r(3) <= sdo(2);
--
-- ISA bus to CS8900
--
t(2) <= isa_a(4);
t(3) <= isa_a(3);
t(4) <= isa_a(2);
t(5) <= isa_a(1);
t(6) <= isa_a(0);
cmp_isa: entity work.sc_isa generic map (
addr_bits => SLAVE_ADDR_BITS
)
port map(
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(5),
wr => sc_wr(5),
rd_data => sc_dout(5),
rdy_cnt => sc_rdy_cnt(5),
isa_d => l(9 downto 2), -- data bus
isa_a => isa_a, -- address bus
isa_reset => l(10), -- reset
isa_nior => t(1), -- nior
isa_niow => l(1) -- niow
);
--
-- IO devices for Mikael and Jens
--
-- microphone input and PWM output
--
cmp_audio: entity work.sc_sigdel generic map (
addr_bits => SLAVE_ADDR_BITS,
fsamp => 8000
)
port map(
clk => clk,
reset => reset,
address => address(SLAVE_ADDR_BITS-1 downto 0),
wr_data => wr_data,
rd => sc_rd(6),
wr => sc_wr(6),
rd_data => sc_dout(6),
rdy_cnt => sc_rdy_cnt(6),
sdi => mic_sdi,
sdo => mic_sdo,
dac => audio_out
);
end rtl;
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