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Message
From: cvs at opencores.org<cvs@o...>
Date: Tue Dec 20 14:20:53 CET 2005
Subject: [cvs-checkins] MODIFIED: simpcon ...
Date: 00/05/12 20:14:20 Modified: simpcon/doc simpcon.pdf simpcon.tex
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Revision Changes Path
1.3 simpcon/doc/simpcon.pdf
http://www.opencores.org/cvsweb.shtml/simpcon/doc/simpcon.pdf?rev=1.3&content-type=text/x-cvsweb-markup
<<Binary file>>
1.2 simpcon/doc/simpcon.tex
http://www.opencores.org/cvsweb.shtml/simpcon/doc/simpcon.tex.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: simpcon.tex
===================================================================
RCS file: /cvsroot/martin/simpcon/doc/simpcon.tex,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- simpcon.tex 28 Nov 2005 15:39:45 -0000 1.1
+++ simpcon.tex 20 Dec 2005 13:20:53 -0000 1.2
@@ -426,14 +426,14 @@
\item SimpCon SRAM interface for JOP on Cyclone and Spartan-3 is
available
\item Project at opencores.org accepted
+ \item Simple UART as SimpCon example
+ \item IO in JOP changed to SimpCon (uart, cnt, usb)
\end{itemize}
%
Next steps:
%
\begin{itemize}
\item Continue this document
- \item Provide more SimpCon examples (e.g.\ a UART)
- \item Change JOPs IO interface to SimpCon
\item Provide Wishbone bridges
\end{itemize}
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