OPENCORES.ORG

  Date: 00/05/12 20:12:40
  Added:       or1k/rc203soc/sw/uClinux/include/asm-mips a.out.h asm.h
                        bitops.h bootinfo.h bugs.h byteorder.h cachectl.h
                        checksum.h delay.h dma.h elf.h errno.h fcntl.h
                        floppy.h fpregdef.h gdb-stub.h io.h ioctl.h
                        ioctls.h irq.h jazz.h jazzdma.h mc146818rtc.h
                        mipsconfig.h mipsregs.h mman.h page.h param.h
                        pgtable.h pica.h processor.h ptrace.h reg.h
                        regdef.h resource.h segment.h shmparam.h
                        sigcontext.h signal.h slots.h socket.h stackframe.h
                        stat.h statfs.h string.h sysmips.h system.h
                        termbits.h termios.h types.h unistd.h user.h
                        vector.h
  Log:
  First Import of RC20x uClinux

  Revision  Changes    Path
  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/a.out.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/a.out.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: a.out.h
  ===================================================================
  #ifndef __ASM_MIPS_A_OUT_H
  #define __ASM_MIPS_A_OUT_H

  struct exec
  {
    unsigned long a_info;		/* Use macros N_MAGIC, etc for access */
    unsigned a_text;		/* length of text, in bytes */
    unsigned a_data;		/* length of data, in bytes */
    unsigned a_bss;		/* length of uninitialized data area for file, in bytes */
    unsigned a_syms;		/* length of symbol table data in file, in bytes */
    unsigned a_entry;		/* start address */
    unsigned a_trsize;		/* length of relocation info for text, in bytes */
    unsigned a_drsize;		/* length of relocation info for data, in bytes */
  };

  #define N_TRSIZE(a)	((a).a_trsize)
  #define N_DRSIZE(a)	((a).a_drsize)
  #define N_SYMSIZE(a)	((a).a_syms)

  #ifdef __KERNEL__

  #define STACK_TOP	TASK_SIZE

  #endif

  #endif /* __ASM_MIPS_A_OUT_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/asm.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/asm.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: asm.h
  ===================================================================
  /*
   * include/asm-mips/asm.h
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1995 by Ralf Baechle
   *
   * Some useful macros for MIPS assembler code
   *
   * Some of the routines below contain useless nops that will be optimized
   * away by gas in -O mode. These nops are however required to fill delay
   * slots in noreorder mode.
   */
  #ifndef	__ASM_ASM_H
  #define	__ASM_ASM_H

  #include <linux/config.h>
  #include <asm/regdef.h>
  #include <asm/fpregdef.h>

  #ifndef CAT
  #ifdef __STDC__
  #define __CAT(str1,str2) str1##str2
  #else
  #define __CAT(str1,str2) str1/**/str2
  #endif
  #define CAT(str1,str2) __CAT(str1,str2)
  #endif

  /*
   * Macros to handle different pointer sizes for 32/64-bit code
   */
  #if __mips == 3
  #define PTR	.quad
  #define PTRSIZE	8
  #define PTRLOG	3
  #define lp	ld
  #else
  #define PTR	.word
  #define PTRSIZE	4
  #define PTRLOG	2
  #define lp	lw
  #endif

  /*
   * ELF specific declarations
   */
  #ifdef __ELF__
  #define TYPE(symbol,_type)                              \
  			.type	symbol, at _type
  #define SIZE(symbol,_size)                              \
  			.size	symbol,_size
  #else
  #define TYPE(symbol,type)
  #define SIZE(symbol,size)
  #endif

  /*
   * PIC specific declarations
   * Not used for the kernel but here seems to be the right place.
   */
  #ifdef __PIC__
  #define CPRESTORE(register)                             \
  			.cprestore register
  #define CPADD(register)                                 \
  			.cpadd	register
  #define CPLOAD(register)                                \
  			.cpload	register
  #else
  #define CPRESTORE(register)
  #define CPADD(register)
  #define CPLOAD(register)
  #endif

  /*
   * LEAF - declare leaf routine
   */
  #define	LEAF(symbol)                                    \
  			.globl	symbol;                 \
  			.align	2;                      \
  			TYPE(symbol,function);          \
  			.ent	symbol,0;               \
  symbol:			.frame	sp,0,ra

  /*
   * NESTED - declare nested routine entry point
   */
  #define	NESTED(symbol, framesize, rpc)                  \
  			.globl	symbol;                 \
  			.align	2;                      \
  			TYPE(symbol,function);          \
  			.ent	symbol,0;               \
  symbol:			.frame	sp, framesize, rpc

  /*
   * END - mark end of function
   */
  #define	END(function)                                   \
  			.end	function;		\
  			SIZE(function,.-function)

  /*
   * EXPORT - export definition of symbol
   */
  #define	EXPORT(symbol)                                  \
  			.globl	symbol;                 \
  symbol:

  /*
   * ABS - export absolute symbol
   */
  #define	ABS(symbol,value)                               \
  			.globl	symbol;                 \
  symbol			=	value

  #define	PANIC(msg)                                      \
  			la	a0,8f;                  \
  			jal	panic;                  \
  			nop;                            \
  9:			b	9b;                     \
  			nop;                            \
  			TEXT(msg)

  /*
   * Print formated string
   */
  #define PRINT(string)                                   \
  			la	a0,8f;                  \
  			jal	printk;                 \
  			nop;                            \
  			TEXT(string)

  #define	TEXT(msg)                                       \
  			.data;                          \
  8:			.asciiz	msg;                    \
  			.text

  /*
   * Build text tables
   */
  #define TTABLE(string)                                  \
  		.text;                                  \
  		.word	1f;                             \
  		.data;                                  \
  1:		.asciz	string;                         \
  		.text;

  /*
   * Move to kernel mode and disable interrupts
   * Set cp0 enable bit as sign that we're running on the kernel stack
   * Use with .set noat!
   * Note that the mtc0 will be effective on R4000 pipeline stage 7. This
   * means that another three instructions will be executed with interrupts
   * disabled.
   */
  #define CLI                                             \
  		mfc0	AT,CP0_STATUS;                  \
  		li	t0,ST0_CU0|0x1f;                \
  		or	AT,t0;                          \
  		xori	AT,0x1f;                        \
  		mtc0	AT,CP0_STATUS;			\

  /*
   * Move to kernel mode and enable interrupts
   * Set cp0 enable bit as sign that we're running on the kernel stack
   * Use with .set noat!
   * Note that the mtc0 will be effective on R4000 pipeline stage 7. This
   * means that another three instructions will be executed with interrupts
   * disabled.  Arch/mips/kernel/r4xx0.S makes use of this fact.
   */
  #define STI                                             \
  		mfc0	AT,CP0_STATUS;                  \
  		li	t0,ST0_CU0|0x1f;                \
  		or	AT,t0;                          \
  		xori	AT,0x1e;                        \
  		mtc0	AT,CP0_STATUS;			\

  /*
   * Special nop to fill load delay slots
   */
  #ifndef __R4000__
  #define NOP     nop
  #else
  #define NOP
  #endif

  /*
   * Return from exception
   */
  #if defined (CONFIG_CPU_R3000)
  #define ERET rfe
  #elif defined (CONFIG_CPU_R4X00) || defined (CONFIG_CPU_R4600)
  #define ERET                                            \
  		.set	mips3;                          \
  		eret;                                   \
  		.set	mips0
  #else
  #error "Implement ERET macro!"
  #endif

  /*
   * R8000/R10000 (MIPS ISA IV) pref instruction.
   * Use with .set noreorder only!
   */
  #if defined (CONFIG_CPU_R8000) || defined(CONFIG_CPU_R10000)
  #define PREF(hint,addr)                                 \
  		pref	hint,addr
  #define PREFX(hint,addr)                                \
  		prefx	hint,addr
  #else
  #define PREF
  #define PREFX
  #endif

  /*
   * R8000/R10000 (MIPS ISA IV) movn/movz instructions and
   * equivalents for old CPUs. Use with .set noreorder only!
   */
  #if defined (CONFIG_CPU_R8000) || defined (CONFIG_CPU_R10000)
  #define MOVN(rd,rs,rt)                                  \
  		movn	rd,rs,rt
  #define MOVZ(rd,rs,rt)                                  \
  		movz	rd,rs,rt
  #elif defined (CONFIG_CPU_R4000) || defined (CONFIG_CPU_R6000)
  #define MOVN(rd,rs,rt)                                  \
  		bnezl	rt,9f                           \
  		move	rd,rs                           \
  9:
  #define MOVZ(rd,rs,rt)                                  \
  		beqzl	rt,9f                           \
  		movz	rd,rt                           \
  9:
  #else /* R2000, R3000 */
  #define MOVN(rd,rs,rt)                                  \
  		beqz	rt,9f                           \
  		nop                                     \
  		move	rd,rs                           \
  9:
  #define MOVZ(rd,rs,rt)                                  \
  		bneqz	rt,9f                           \
  		nop                                     \
  		movz	rd,rt                           \
  9:
  #endif

  #endif /* __ASM_ASM_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/bitops.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/bitops.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: bitops.h
  ===================================================================
  /*
   * include/asm-mips/bitops.h
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (c) 1994, 1995  Ralf Baechle
   */
  #ifndef __ASM_MIPS_BITOPS_H
  #define __ASM_MIPS_BITOPS_H

  #if __mips > 1

  /*
   * These functions for MIPS ISA >= 2 are interrupt and SMP proof and
   * interrupt friendly
   */
  #include <asm/mipsregs.h>

  /*
   * The following functions will only work for the R4000!
   */
  extern __inline__ int set_bit(int nr, void *addr)
  {
  	int	mask, retval, mw;

  	addr += ((nr >> 3) & ~3);
  	mask = 1 << (nr & 0x1f);
  	do {
  		mw = load_linked(addr);
  		retval = (mask & mw) != 0;
  		}
  	while (!store_conditional(addr, mw|mask));

  	return retval;
  }

  extern __inline__ int clear_bit(int nr, void *addr)
  {
  	int	mask, retval, mw;

  	addr += ((nr >> 3) & ~3);
  	mask = 1 << (nr & 0x1f);
  	do {
  		mw = load_linked(addr);
  		retval = (mask & mw) != 0;
  		}
  	while (!store_conditional(addr, mw & ~mask));

  	return retval;
  }

  extern __inline__ int change_bit(int nr, void *addr)
  {
  	int	mask, retval, mw;

  	addr += ((nr >> 3) & ~3);
  	mask = 1 << (nr & 0x1f);
  	do {
  		mw = load_linked(addr);
  		retval = (mask & mw) != 0;
  		}
  	while (!store_conditional(addr, mw ^ mask));

  	return retval;
  }

  #else /* __mips <= 1 */

  /*
   * These functions are only used for MIPS ISA 1 CPUs.  Since I don't
   * believe that someone ever will run Linux/SMP on such a beast I don't
   * worry about making them SMP proof.
   */
  #include <asm/system.h>

  #ifdef __KERNEL__
  /*
   * Only disable interrupt for kernel mode stuff to keep usermode stuff
   * that dares to use kernel include files alive.
   */
  #define __flags unsigned long flags
  #define __cli() cli()
  #define __save_flags(x) save_flags(x)
  #define __restore_flags(x) restore_flags(x)
  #endif /* __KERNEL__ */

  extern __inline__ int set_bit(int nr, void * addr)
  {
  	int	mask, retval;
  	int	*a = addr;
  	__flags;

  	a += nr >> 5;
  	mask = 1 << (nr & 0x1f);
  	__save_flags(flags);
  	__cli();
  	retval = (mask & *a) != 0;
  	*a |= mask;
  	__restore_flags(flags);

  	return retval;
  }

  extern __inline__ int clear_bit(int nr, void * addr)
  {
  	int	mask, retval;
  	int	*a = addr;
  	__flags;

  	a += nr >> 5;
  	mask = 1 << (nr & 0x1f);
  	__save_flags(flags);
  	__cli();
  	retval = (mask & *a) != 0;
  	*a &= ~mask;
  	__restore_flags(flags);

  	return retval;
  }

  extern __inline__ int change_bit(int nr, void * addr)
  {
  	int	mask, retval;
  	int	*a = addr;
  	__flags;

  	a += nr >> 5;
  	mask = 1 << (nr & 0x1f);
  	__save_flags(flags);
  	__cli();
  	retval = (mask & *a) != 0;
  	*a ^= mask;
  	__restore_flags(flags);

  	return retval;
  }

  #undef __flags
  #undef __cli()
  #undef __save_flags(x)
  #undef __restore_flags(x)

  #endif /* __mips <= 1 */

  extern __inline__ int test_bit(int nr, const void *addr)
  {
  	return 1UL & (((const unsigned int *) addr)[nr >> 5] >> (nr & 31));
  }

  extern __inline__ int find_first_zero_bit (void *addr, unsigned size)
  {
  	int res;

  	if (!size)
  		return 0;

  	__asm__(".set\tnoreorder\n\t"
  		".set\tnoat\n"
  		"1:\tsubu\t$1,%2,%0\n\t"
  		"blez\t$1,2f\n\t"
  		"lw\t$1,(%4)\n\t"
  		"addiu\t%4,%4,4\n\t"
  		"beql\t%1,$1,1b\n\t"
  		"addiu\t%0,%0,32\n\t"
  		"li\t%1,1\n"
  		"1:\tand\t%4,$1,%1\n\t"
  		"beq\t$0,%4,2f\n\t"
  		"sll\t%1,%1,1\n\t"
  		"bne\t$0,%1,1b\n\t"
  		"add\t%0,%0,1\n\t"
  		".set\tat\n\t"
  		".set\treorder\n"
  		"2:"
  		: "=r" (res)
  		: "r" ((unsigned int) 0xffffffff),
  		  "r" (size),
  		  "0" ((signed int) 0),
  		  "r" (addr)
  		: "$1");

  	return res;
  }

  extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
  {
  	unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
  	int set = 0, bit = offset & 31, res;

  	if (bit) {
  		/*
  		 * Look for zero in first byte
  		 */
  		__asm__(".set\tnoreorder\n\t"
  			".set\tnoat\n"
  			"1:\tand\t$1,%2,%1\n\t"
  			"beq\t$0,$1,2f\n\t"
  			"sll\t%2,%2,1\n\t"
  			"bne\t$0,%2,1b\n\t"
  			"addiu\t%0,%0,1\n\t"
  			".set\tat\n\t"
  			".set\treorder\n"
  			: "=r" (set)
  			: "r" (*p >> bit),
  			  "r" (1),
  			  "0" (0)
  			: "$1");
  		if (set < (32 - bit))
  			return set + offset;
  		set = 32 - bit;
  		p++;
  	}
  	/*
  	 * No zero yet, search remaining full bytes for a zero
  	 */
  	res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
  	return (offset + set + res);
  }

  /*
   * ffz = Find First Zero in word. Undefined if no zero exists,
   * so code should check against ~0UL first..
   */
  extern __inline__ unsigned long ffz(unsigned long word)
  {
  	unsigned int	__res;
  	unsigned int	mask = 1;

  	__asm__ __volatile__ (
  		".set\tnoreorder\n\t"
  		".set\tnoat\n\t"
  		"move\t%0,$0\n"
  		"1:\tand\t$1,%2,%1\n\t"
  		"beqz\t$1,2f\n\t"
  		"sll\t%1,1\n\t"
  		"bnez\t%1,1b\n\t"
  		"addiu\t%0,1\n\t"
  		".set\tat\n\t"
  		".set\treorder\n"
  		"2:\n\t"
  		: "=r" (__res), "=r" (mask)
  		: "r" (word), "1" (mask)
  		: "$1");

  	return __res;
  }

  #endif /* __ASM_MIPS_BITOPS_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/bootinfo.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/bootinfo.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: bootinfo.h
  ===================================================================
  /*
   * bootinfo.h -- Definition of the Linux/MIPS boot information structure
   *
   * Copyright (C) 1994 by Waldorf Electronics
   * Written by Ralf Baechle and Andreas Busse
   *
   * Based on Linux/68k linux/include/linux/bootstrap.h
   * Copyright (C) 1992 by Greg Harp
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file README.legal in the main directory of this archive
   * for more details.
   */
  #ifndef __ASM_MIPS_BOOTINFO_H
  #define __ASM_MIPS_BOOTINFO_H

  /*
   * Valid machtype values
   */
  #define MACH_UNKNOWN		0		/* whatever...               */
  #define MACH_DESKSTATION_RPC44  1               /* Deskstation rPC44         */
  #define MACH_DESKSTATION_TYNE	2		/* Deskstation Tyne          */
  #define MACH_ACER_PICA_61	3		/* Acer PICA-61 (PICA1)      */
  #define MACH_MIPS_MAGNUM_4000	4		/* Mips Magnum 4000 "RC4030" */
  #define MACH_OLIVETTI_M700      5               /* Olivetti M700 */
  #define MACH_LAST               5

  #define MACH_NAMES { "unknown", "Deskstation rPC44", "Deskstation Tyne", \
  	"Acer PICA 61", "Mips Magnum 4000", "Olivetti M700" }

  /*
   * Valid cputype values
   */
  #define CPU_UNKNOWN		0
  #define CPU_R2000		1
  #define CPU_R3000		2
  #define CPU_R3000A		3
  #define CPU_R3041		4
  #define CPU_R3051		5
  #define CPU_R3052		6
  #define CPU_R3081		7
  #define CPU_R3081E		8
  #define CPU_R4000PC		9
  #define CPU_R4000SC		10
  #define CPU_R4000MC		11
  #define CPU_R4200		12
  #define CPU_R4400PC		13
  #define CPU_R4400SC		14
  #define CPU_R4400MC		15
  #define CPU_R4600		16
  #define CPU_R6000		17
  #define CPU_R6000A		18
  #define CPU_R8000		19
  #define CPU_R10000		20
  #define CPU_LAST                20

  #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
          "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC",         \
          "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000",          \
          "R6000A", "R8000", "R10000" }

  #define CL_SIZE      (80)

  #ifndef __LANGUAGE_ASSEMBLY__

  /*
   * Some machine parameters passed by MILO. Note that bootinfo
   * *must* be in the data segment since the kernel clears the
   * bss segment directly after startup.
   */

  struct drive_info_struct {
  	char dummy[32];
  	};

  struct bootinfo {
  	/*
  	 * machine type
  	 */
  	unsigned long machtype;

  	/*
  	 * system CPU & FPU
  	 */
  	unsigned long cputype;

  	/*
  	 * Installed RAM
  	 */
  	unsigned long memlower;
  	unsigned long memupper;

  	/*
  	 * Cache Sizes (0xffffffff = unknown)
  	 */
  	unsigned long icache_size;
  	unsigned long icache_linesize;
  	unsigned long dcache_size;
  	unsigned long dcache_linesize;
  	unsigned long scache_size;
  	unsigned long scache_linesize;

  	/*
  	 * TLB Info
  	 */
  	unsigned long tlb_entries;

  	/*
  	 * DMA buffer size (Deskstation only)
  	 */
  	unsigned long dma_cache_size;
  	unsigned long dma_cache_base;

  	/*
  	 * Ramdisk Info
  	 */
  	unsigned long ramdisk_flags;		/* ramdisk flags */
  	unsigned long ramdisk_base;		/* address of the ram disk in mem */

  	/*
  	 * Boot flags for the kernel
  	 */
  	unsigned long mount_root_rdonly;
  	struct drive_info_struct drive_info;

  	/*
  	 * Video ram info (not in tty.h)
  	 */
  	unsigned long vram_base;		/* video ram base address */

  	char command_line[CL_SIZE];		/* kernel command line parameters */

  };

  #if 0
  /*
   * New style bootinfo
   *
   * Add new tags only at the end of the enum; *never* remove any tags
   * or you'll break compatibility!
   */
  enum bi_tag {	
  	/*
  	 * not a real tag
  	 */
  	dummy,

  	/*
  	 * machine type
  	 */
  	machtype,

  	/*
  	 * system CPU & FPU
  	 */
  	cputype,

  	/*
  	 * Installed RAM
  	 */
  	memlower,
  	memupper,

  	/*
  	 * Cache Sizes (0xffffffff = unknown)
  	 */
  	icache_size,
  	icache_linesize,
  	dcache_size,
  	dcache_linesize,
  	scache_size,
  	scache_linesize,

  	/*
  	 * TLB Info
  	 */
  	tlb_entries,

  	/*
  	 * DMA buffer size (Deskstation only)
  	 */
  	dma_cache_size,
  	dma_cache_base,

  	/*
  	 * Ramdisk Info
  	 */
  	ramdisk_size,		/* ramdisk size in 1024 byte blocks */
  	ramdisk_base,		/* address of the ram disk in mem */

  	/*
  	 * Boot flags for the kernel
  	 */
  	mount_root_rdonly,
  	drive_info,

  	/*
  	 * Video ram info (not in tty.h)
  	 */
  	vram_base,		/* video ram base address */

  	command_line		/* kernel command line parameters */

  };

  typedef struct {
  	bi_tag		tag;
  	unsigned long	size;
  } tag;
  #endif

  extern struct bootinfo boot_info;

  /*
   * Defaults, may be overwritten by milo. We initialize
   * them to make sure that both boot_info and screen_info
   * are in the .data segment since the .bss segment is
   * cleared during startup.
   */
  #define BOOT_INFO { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, {{0,}}, 0, "" }
  #define SCREEN_INFO {0, 0, {0, }, 52, 3, 80, 4626, 3, 9, 50}

  #else /* !__LANGUAGE_ASSEMBLY__ */

  /*
   * Same structure, but as offsets for usage within assembler source.
   * Don't mess with struct bootinfo without changing offsets too!
   */

  #define OFFSET_BOOTINFO_MACHTYPE           0
  #define OFFSET_BOOTINFO_CPUTYPE            4
  #define OFFSET_BOOTINFO_MEMLOWER           8
  #define OFFSET_BOOTINFO_MEMUPPER          12
  #define OFFSET_BOOTINFO_ICACHE_SIZE       16
  #define OFFSET_BOOTINFO_ICACHE_LINESIZE   20
  #define OFFSET_BOOTINFO_DCACHE_SIZE       24
  #define OFFSET_BOOTINFO_DCACHE_LINESIZE   28
  #define OFFSET_BOOTINFO_SCACHE_SIZE       32
  #define OFFSET_BOOTINFO_SCACHE_LINESIZE   36
  #define OFFSET_BOOTINFO_TLB_ENTRIES       40
  #define OFFSET_BOOTINFO_DMA_CACHE_SIZE    44
  #define OFFSET_BOOTINFO_DMA_CACHE_BASE    48
  #define OFFSET_BOOTINFO_RAMDISK_SIZE      52
  #define OFFSET_BOOTINFO_RAMDISK_BASE      56
  #define OFFSET_BOOTINFO_MOUNT_RD_ONLY     60
  #define OFFSET_BOOTINFO_DRIVE_INFO        64
  #define OFFSET_BOOTINFO_VRAM_BASE         96
  #define OFFSET_BOOTINFO_COMMAND_LINE      100

  #endif /* __LANGUAGE_ASSEMBLY__ */

  #endif /* __ASM_MIPS_BOOTINFO_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/bugs.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/bugs.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: bugs.h
  ===================================================================
  /*
   *  include/asm-mips/bugs.h
   *
   *  Copyright (C) 1995  Waldorf Electronics
   *  written by Ralf Baechle
   */
  #include <asm/bootinfo.h>

  /*
   * This is included by init/main.c to check for architecture-dependent bugs.
   *
   * Needs:
   *	void check_bugs(void);
   */

  extern struct bootinfo boot_info;

  static void check_wait(void)
  {
  	printk("Checking for 'wait' instruction... ");
  	switch(boot_info.cputype) {
  		case CPU_R4200: 
  		case CPU_R4600: 
  			wait_available = 1;
  			printk(" available.\n");
  			break;
  		default:
  			printk(" unavailable.\n");
  			break;
  		}
  }

  static void check_bugs(void)
  {
  	check_wait();
  }

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/byteorder.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/byteorder.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: byteorder.h
  ===================================================================
  #ifndef __ASM_MIPS_BYTEORDER_H
  #define __ASM_MIPS_BYTEORDER_H

  /*
   * FIXME: Add big endian support
   */
  #undef ntohl
  #undef ntohs
  #undef htonl
  #undef htons

  #if defined (__MIPSEL__)
  #define __LITTLE_ENDIAN
  #define __LITTLE_ENDIAN_BITFIELD
  #elif defined (__MIPSEB__)
  #define __BIG_ENDIAN
  #define __BIG_ENDIAN_BITFIELD
  #else
  #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
  #endif

  extern unsigned long int	ntohl(unsigned long int);
  extern unsigned short int	ntohs(unsigned short int);
  extern unsigned long int	htonl(unsigned long int);
  extern unsigned short int	htons(unsigned short int);

  extern __inline__ unsigned long int	__ntohl(unsigned long int);
  extern __inline__ unsigned short int	__ntohs(unsigned short int);
  extern __inline__ unsigned long int	__constant_ntohl(unsigned long int);
  extern __inline__ unsigned short int	__constant_ntohs(unsigned short int);

  /*
   * The constant and non-constant versions here are the same.
   * Maybe I'll come up with an mips-optimized routine for the
   * non-constant ones (the constant ones don't need it: gcc
   * will optimize it to the correct constant).  Oh, and the
   * big endian routines that are still missing will be fairly
   * easy to write :-)
   */

  extern __inline__ unsigned long int
  __ntohl(unsigned long int x)
  {
  	return (((x & 0x000000ffU) << 24) |
  		((x & 0x0000ff00U) <<  8) |
  		((x & 0x00ff0000U) >>  8) |
  		((x & 0xff000000U) >> 24));
  }

  #define __constant_ntohl(x) \
  	((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \
  			     (((unsigned long int)(x) & 0x0000ff00U) <<  8) | \
  			     (((unsigned long int)(x) & 0x00ff0000U) >>  8) | \
  			     (((unsigned long int)(x) & 0xff000000U) >> 24)))

  extern __inline__ unsigned short int
  __ntohs(unsigned short int x)
  {
  	return (((x & 0x00ff) << 8) |
  		((x & 0xff00) >> 8));
  }

  #define __constant_ntohs(x) \
  	((unsigned short int)((((unsigned short int)(x) & 0x00ff) << 8) | \
  			      (((unsigned short int)(x) & 0xff00) >> 8))) \

  #define __htonl(x) __ntohl(x)
  #define __htons(x) __ntohs(x)
  #define __constant_htonl(x) __constant_ntohl(x)
  #define __constant_htons(x) __constant_ntohs(x)

  #ifdef  __OPTIMIZE__
  #  define ntohl(x) \
  (__builtin_constant_p((long)(x)) ? \
   __constant_ntohl((x)) : \
   __ntohl((x)))
  #  define ntohs(x) \
  (__builtin_constant_p((short)(x)) ? \
   __constant_ntohs((x)) : \
   __ntohs((x)))
  #  define htonl(x) \
  (__builtin_constant_p((long)(x)) ? \
   __constant_htonl((x)) : \
   __htonl((x)))
  #  define htons(x) \
  (__builtin_constant_p((short)(x)) ? \
   __constant_htons((x)) : \
   __htons((x)))
  #endif

  #endif /* __ASM_MIPS_BYTEORDER_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/cachectl.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/cachectl.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: cachectl.h
  ===================================================================
  /*
   * include/asm-mips/cachectl.h
   *
   * Written by Ralf Baechle,
   * Copyright (C) 1994 by Waldorf GMBH
   */
  #ifndef	__ASM_MIPS_CACHECTL
  #define	__ASM_MIPS_CACHECTL

  /*
   * cachectl.h -- defines for MIPS cache control system calls
   */

  /*
   * Options for cacheflush system call
   */
  #define	ICACHE	(1<<0)		/* flush instruction cache        */
  #define	DCACHE	(1<<1)		/* writeback and flush data cache */
  #define	BCACHE	(ICACHE|DCACHE)	/* flush both caches              */

  #ifdef __KERNEL__
  #define CACHELINES      512	/* number of cachelines (kludgy)  */

  /*
   * Cache Operations - for use by assembler code
   */
  #define Index_Invalidate_I      0x00
  #define Index_Writeback_Inv_D   0x01
  #define Index_Load_Tag_D        0x05

  #ifndef __LANGUAGE_ASSEMBLY__

  extern int sys_cacheflush(void *addr, int nbytes, int cache);

  #endif /* !__LANGUAGE_ASSEMBLY__ */
  #endif   /* __KERNEL__ */
  #endif	/* __ASM_MIPS_CACHECTL */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/checksum.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/checksum.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: checksum.h
  ===================================================================
  /*
   * include/asm-mips/checksum.h
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1995 by Ralf Baechle
   */
  #ifndef __ASM_MIPS_CHECKSUM_H
  #define __ASM_MIPS_CHECKSUM_H

  /*
   * computes the checksum of a memory block at buff, length len,
   * and adds in "sum" (32-bit)
   *
   * returns a 32-bit number suitable for feeding into itself
   * or csum_tcpudp_magic
   *
   * this function must be called with even lengths, except
   * for the last fragment, which may be odd
   *
   * it's best to have buff aligned on a 32-bit boundary
   */
  unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);

  /*
   * the same as csum_partial, but copies from src while it
   * checksums
   *
   * here even more important to align src and dst on a 32-bit (or even
   * better 64-bit) boundary
   */
  unsigned int csum_partial_copy(const char *src, char *dst, int len, int sum);

  /*
   * the same as csum_partial, but copies from user space (but on the alpha
   * we have just one address space, so this is identical to the above)
   */
  #define csum_partial_copy_fromuser csum_partial_copy

  /*
   *	This is a version of ip_compute_csum() optimized for IP headers,
   *	which always checksum on 4 octet boundaries.
   *
   *	By Jorge Cwik <jorge@l...>, adapted for linux by
   *	Arnt Gulbrandsen.
   */
  static inline unsigned short ip_fast_csum(unsigned char * iph,
  					  unsigned int ihl)
  {
  	unsigned short int sum;
  	unsigned long	dummy1, dummy2;

  	/*
  	 * This is optimized for 32-bit MIPS processors.
  	 * I tried it in plain C but the generated code looks to bad to
  	 * use with old first generation MIPS CPUs.
  	 * Using 64-bit code could even further improve these routines.
  	 */
  	__asm__("
  	.set	noreorder
  	.set	noat
  	lw	%0,(%3)
  	subu	%1,4
  	blez	%1,2f
  	sll	%1,%4,2			# delay slot
  	lw	%2,4(%3)
  	addu	%1,%3			# delay slot
  	addu	%0,%2
  	sltu	$1,%0,%2
  	lw	%2,8(%3)
  	addu	%0,$1
  	addu	%0,%2
  	sltu	$1,%0,%2
  	lw	%2,12(%3)
  	addu	%0,$1
  	addu	%0,%2
  	sltu	$1,%0,%2
  	addu	%0,$1
  1:	lw	%2,16(%3)
  	addu	%1,4
  	addu	%0,%2
  	sltu	$1,%0,%2
  	bne	%1,%3,1b
  	addu	%0,$1			# delay slot
  	srl	$1,%0,16
  	addu	%0,$1
  	sltu	$1,%0,$1
  	addu	%0,$1
  	nor	%0,$0,%0
  	andi	%0,0xffff
  2:	.set	at
  	.set	reorder"
  	: "=r" (sum), "=r" (dummy1), "=r" (dummy2)
  	: "r" (iph), "r"(ihl)
  	: "$1");

  	return sum;
  }

  /*
   * computes the checksum of the TCP/UDP pseudo-header
   * returns a 16-bit checksum, already complemented
   */
  static inline unsigned short int csum_tcpudp_magic(unsigned long saddr,
  						   unsigned long daddr,
  						   unsigned short len,
  						   unsigned short proto,
  						   unsigned int sum)
  {
      __asm__("
  	.set	noat
  	addu	%0,%2
  	sltu	$1,%0,%2
  	addu	%0,$1
  	addu	%0,%3
  	sltu	$1,%0,%3
  	addu	%0,$1
  	addu	%0,%4
  	sltu	$1,%0,%4
  	addu	%0,$1
  	srl	$1,%0,16
  	addu	%0,$1
  	sltu	$1,%0,$1
  	addu	%0,$1
  	nor	%0,$0,%0
  	andi	%0,0xffff
  	.set	at"
  	: "=r" (sum)
  	: "0" (daddr), "r"(saddr), "r"((ntohs(len)<<16)+proto*256), "r"(sum)
  	: "$1");

  	return (unsigned short)sum;
  }

  /*
   *	Fold a partial checksum without adding pseudo headers
   */
  static inline unsigned short int csum_fold(unsigned int sum)
  {
      __asm__("
  	.set	noat
  	srl	$1,%0,16
  	addu	%0,$1
  	sltu	$1,%0,$1
  	nor	%0,$0,%0
  	andi	%0,0xffff
  	.set	at"
  	: "=r"(sum)
  	: "0" (sum)
  	: "$1");

   	return sum;
  }

  /*
   * this routine is used for miscellaneous IP-like checksums, mainly
   * in icmp.c
   */
  static inline unsigned short ip_compute_csum(unsigned char * buff, int len) {
      unsigned short int sum;

      __asm__("
  	.set	noat
  	srl	$1,%0,16
  	addu	%0,$1
  	sltu	$1,%0,$1
  	nor	%0,$0,%0
  	andi	%0,0xffff
  	.set	at"
  	: "=r"(sum)
  	: "r" (csum_partial(buff, len, 0))
  	: "$1");

  	return sum;
  }

  #endif /* __ASM_MIPS_CHECKSUM_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/delay.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/delay.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: delay.h
  ===================================================================
  #ifndef __ASM_MIPS_DELAY_H
  #define __ASM_MIPS_DELAY_H

  extern __inline__ void __delay(int loops)
  {
  	__asm__ __volatile__ (
  		".set\tnoreorder\n\t"
  		".set\tnoat\n\t"
  		"1:\tbne\t$0,%0,1b\n\t"
  		"subu\t%0,%0,1\n\t"
  		".set\tat\n\t"
  		".set\treorder"
  		:"=r" (loops)
  		:"0" (loops));
  }

  /*
   * division by multiplication: you don't have to worry about
   * loss of precision.
   *
   * Use only for very small delays ( < 1 msec).  Should probably use a
   * lookup table, really, as the multiplications take much too long with
   * short delays.  This is a "reasonable" implementation, though (and the
   * first constant multiplications gets optimized away if the delay is
   * a constant)
   */
  extern __inline__ void udelay(unsigned long usecs)
  {
  	usecs *= 0x000010c6;		/* 2**32 / 1000000 */
  	__asm__("multu\t%0,%1\n\t"
  		"mfhi\t%0"
  		:"=r" (usecs)
  		:"0" (usecs),"r" (loops_per_sec));
  	__delay(usecs);
  }

  /*
   * The different variants for 32/64 bit are pure paranoia. The typical
   * range of numbers that appears for MIPS machines avoids overflows.
   */
  extern __inline__ unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c)
  {
  	return (a*b)/c;
  }

  #endif /* __ASM_MIPS_DELAY_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/dma.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/dma.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: dma.h
  ===================================================================
  /* $Id: dma.h,v 1.1 2005/12/20 11:40:42 jcastillo Exp $
   * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   * Written by Hennus Bergman, 1992.
   * High DMA channel support & info by Hannu Savolainen
   * and John Boyd, Nov. 1992.
   *
   * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
   * and can only be used for expansion cards. Onboard DMA controller, such
   * as the R4030 on Jazz boards behave totally different!
   */

  #ifndef __ASM_MIPS_DMA_H
  #define __ASM_MIPS_DMA_H

  #include <asm/io.h>		/* need byte IO */

  #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  #define dma_outb	outb_p
  #else
  #define dma_outb	outb
  #endif

  #define dma_inb		inb

  /*
   * NOTES about DMA transfers:
   *
   *  controller 1: channels 0-3, byte operations, ports 00-1F
   *  controller 2: channels 4-7, word operations, ports C0-DF
   *
   *  - ALL registers are 8 bits only, regardless of transfer size
   *  - channel 4 is not used - cascades 1 into 2.
   *  - channels 0-3 are byte - addresses/counts are for physical bytes
   *  - channels 5-7 are word - addresses/counts are for physical words
   *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
   *  - transfer count loaded to registers is 1 less than actual count
   *  - controller 2 offsets are all even (2x offsets for controller 1)
   *  - page registers for 5-7 don't use data bit 0, represent 128K pages
   *  - page registers for 0-3 use bit 0, represent 64K pages
   *
   * DMA transfers are limited to the lower 16MB of _physical_ memory.  
   * Note that addresses loaded into registers must be _physical_ addresses,
   * not logical addresses (which may differ if paging is active).
   *
   *  Address mapping for channels 0-3:
   *
   *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
   *    |  ...  |   |  ... |   |  ... |
   *    |  ...  |   |  ... |   |  ... |
   *    |  ...  |   |  ... |   |  ... |
   *   P7  ...  P0  A7 ... A0  A7 ... A0   
   * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
   *
   *  Address mapping for channels 5-7:
   *
   *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
   *    |  ...  |   \   \   ... \  \  \  ... \  \
   *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
   *    |  ...  |     \   \   ... \  \  \  ... \
   *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
   * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
   *
   * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
   * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
   * the hardware level, so odd-byte transfers aren't possible).
   *
   * Transfer count (_not # bytes_) is limited to 64K, represented as actual
   * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
   * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
   *
   */

  #define MAX_DMA_CHANNELS	8

  /*
   * The maximum address that we can perform a DMA transfer to on this platform
   * This describes only the PC style part of the DMA logic like on Deskstations
   * or Acer PICA but not the much more versatile DMA logic used for the
   * local devices on Acer PICA or Magnums.
   */
  #define MAX_DMA_ADDRESS		0x1000000

  /* 8237 DMA controllers */
  #define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
  #define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */

  /* DMA controller registers */
  #define DMA1_CMD_REG		0x08	/* command register (w) */
  #define DMA1_STAT_REG		0x08	/* status register (r) */
  #define DMA1_REQ_REG            0x09    /* request register (w) */
  #define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
  #define DMA1_MODE_REG		0x0B	/* mode register (w) */
  #define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
  #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  #define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
  #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
  #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */

  #define DMA2_CMD_REG		0xD0	/* command register (w) */
  #define DMA2_STAT_REG		0xD0	/* status register (r) */
  #define DMA2_REQ_REG            0xD2    /* request register (w) */
  #define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
  #define DMA2_MODE_REG		0xD6	/* mode register (w) */
  #define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
  #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
  #define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
  #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
  #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */

  #define DMA_ADDR_0              0x00    /* DMA address registers */
  #define DMA_ADDR_1              0x02
  #define DMA_ADDR_2              0x04
  #define DMA_ADDR_3              0x06
  #define DMA_ADDR_4              0xC0
  #define DMA_ADDR_5              0xC4
  #define DMA_ADDR_6              0xC8
  #define DMA_ADDR_7              0xCC

  #define DMA_CNT_0               0x01    /* DMA count registers */
  #define DMA_CNT_1               0x03
  #define DMA_CNT_2               0x05
  #define DMA_CNT_3               0x07
  #define DMA_CNT_4               0xC2
  #define DMA_CNT_5               0xC6
  #define DMA_CNT_6               0xCA
  #define DMA_CNT_7               0xCE

  #define DMA_PAGE_0              0x87    /* DMA page registers */
  #define DMA_PAGE_1              0x83
  #define DMA_PAGE_2              0x81
  #define DMA_PAGE_3              0x82
  #define DMA_PAGE_5              0x8B
  #define DMA_PAGE_6              0x89
  #define DMA_PAGE_7              0x8A

  #define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
  #define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
  #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */

  /* enable/disable a specific DMA channel */
  static __inline__ void enable_dma(unsigned int dmanr)
  {
  	if (dmanr<=3)
  		dma_outb(dmanr,  DMA1_MASK_REG);
  	else
  		dma_outb(dmanr & 3,  DMA2_MASK_REG);
  }

  static __inline__ void disable_dma(unsigned int dmanr)
  {
  	if (dmanr<=3)
  		dma_outb(dmanr | 4,  DMA1_MASK_REG);
  	else
  		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
  }

  /* Clear the 'DMA Pointer Flip Flop'.
   * Write 0 for LSB/MSB, 1 for MSB/LSB access.
   * Use this once to initialize the FF to a known state.
   * After that, keep track of it. :-)
   * --- In order to do that, the DMA routines below should ---
   * --- only be used while interrupts are disabled! ---
   */
  static __inline__ void clear_dma_ff(unsigned int dmanr)
  {
  	if (dmanr<=3)
  		dma_outb(0,  DMA1_CLEAR_FF_REG);
  	else
  		dma_outb(0,  DMA2_CLEAR_FF_REG);
  }

  /* set mode (above) for a specific DMA channel */
  static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
  {
  	if (dmanr<=3)
  		dma_outb(mode | dmanr,  DMA1_MODE_REG);
  	else
  		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
  }

  /* Set only the page register bits of the transfer address.
   * This is used for successive transfers when we know the contents of
   * the lower 16 bits of the DMA current address register, but a 64k boundary
   * may have been crossed.
   */
  static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
  {
  	switch(dmanr) {
  		case 0:
  			dma_outb(pagenr, DMA_PAGE_0);
  			break;
  		case 1:
  			dma_outb(pagenr, DMA_PAGE_1);
  			break;
  		case 2:
  			dma_outb(pagenr, DMA_PAGE_2);
  			break;
  		case 3:
  			dma_outb(pagenr, DMA_PAGE_3);
  			break;
  		case 5:
  			dma_outb(pagenr & 0xfe, DMA_PAGE_5);
  			break;
  		case 6:
  			dma_outb(pagenr & 0xfe, DMA_PAGE_6);
  			break;
  		case 7:
  			dma_outb(pagenr & 0xfe, DMA_PAGE_7);
  			break;
  	}
  }

  /* Set transfer address & page bits for specific DMA channel.
   * Assumes dma flipflop is clear.
   */
  static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
  {
  	set_dma_page(dmanr, a>>16);
  	if (dmanr <= 3)  {
  	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
              dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
  	}  else  {
  	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
  	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
  	}
  }

  /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
   * a specific DMA channel.
   * You must ensure the parameters are valid.
   * NOTE: from a manual: "the number of transfers is one more
   * than the initial word count"! This is taken into account.
   * Assumes dma flip-flop is clear.
   * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
   */
  static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
  {
          count--;
  	if (dmanr <= 3)  {
  	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
  	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
          } else {
  	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
  	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
          }
  }

  /* Get DMA residue count. After a DMA transfer, this
   * should return zero. Reading this while a DMA transfer is
   * still in progress will return unpredictable results.
   * If called before the channel has been used, it may return 1.
   * Otherwise, it returns the number of _bytes_ left to transfer.
   *
   * Assumes DMA flip-flop is clear.
   */
  static __inline__ int get_dma_residue(unsigned int dmanr)
  {
  	unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
  					 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;

  	/* using short to get 16-bit wrap around */
  	unsigned short count;

  	count = 1 + dma_inb(io_port);
  	count += dma_inb(io_port) << 8;

  	return (dmanr<=3)? count : (count<<1);
  }

  /* These are in kernel/dma.c: */
  extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */
  extern void free_dma(unsigned int dmanr);	/* release it again */

  /*
   * DMA memory allocation - formerly in include/linux/mm.h
   */
  #define __get_dma_pages(priority, order) __get_free_pages((priority),(order), 1)

  #endif /* __ASM_MIPS_DMA_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/elf.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/elf.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: elf.h
  ===================================================================
  #ifndef __ASM_MIPS_ELF_H
  #define __ASM_MIPS_ELF_H

  /*
   * ELF register definitions
   * This is "make it compile" stuff!
   */
  #define ELF_NGREG	32
  #define ELF_NFPREG	32

  typedef unsigned long elf_greg_t;
  typedef elf_greg_t elf_gregset_t[ELF_NGREG];

  typedef double elf_fpreg_t;
  typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];

  /*
   * This is used to ensure we don't load something for the wrong architecture.
   */
  #define elf_check_arch(x) ((x) == EM_MIPS)

  /*
   * These are used to set parameters in the core dumps.
   * FIXME(eric) I don't know what the correct endianness to use is.
   */
  #define ELF_CLASS	ELFCLASS32
  #define ELF_DATA	ELFDATA2MSB;
  #define ELF_ARCH	EM_MIPS

  #define USE_ELF_CORE_DUMP
  #define ELF_EXEC_PAGESIZE	4096

  #endif /* __ASM_MIPS_ELF_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/errno.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/errno.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: errno.h
  ===================================================================
  /*
   * include/asm-mips/errno.h
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1995 by Ralf Baechle
   */
  #ifndef __ASM_MIPS_ERRNO_H
  #define __ASM_MIPS_ERRNO_H

  /*
   * These error numbers are intended to be MIPS ABI compatible
   */
  #define	EPERM		 1	/* Operation not permitted */
  #define	ENOENT		 2	/* No such file or directory */
  #define	ESRCH		 3	/* No such process */
  #define	EINTR		 4	/* Interrupted system call */
  #define	EIO		 5	/* I/O error */
  #define	ENXIO		 6	/* No such device or address */
  #define	E2BIG		 7	/* Arg list too long */
  #define	ENOEXEC		 8	/* Exec format error */
  #define	EBADF		 9	/* Bad file number */
  #define	ECHILD		10	/* No child processes */
  #define	EAGAIN		11	/* Try again */
  #define	ENOMEM		12	/* Out of memory */
  #define	EACCES		13	/* Permission denied */
  #define	EFAULT		14	/* Bad address */
  #define	ENOTBLK		15	/* Block device required */
  #define	EBUSY		16	/* Device or resource busy */
  #define	EEXIST		17	/* File exists */
  #define	EXDEV		18	/* Cross-device link */
  #define	ENODEV		19	/* No such device */
  #define	ENOTDIR		20	/* Not a directory */
  #define	EISDIR		21	/* Is a directory */
  #define	EINVAL		22	/* Invalid argument */
  #define	ENFILE		23	/* File table overflow */
  #define	EMFILE		24	/* Too many open files */
  #define	ENOTTY		25	/* Not a typewriter */
  #define	ETXTBSY		26	/* Text file busy */
  #define	EFBIG		27	/* File too large */
  #define	ENOSPC		28	/* No space left on device */
  #define	ESPIPE		29	/* Illegal seek */
  #define	EROFS		30	/* Read-only file system */
  #define	EMLINK		31	/* Too many links */
  #define	EPIPE		32	/* Broken pipe */
  #define	EDOM		33	/* Math argument out of domain of func */
  #define	ERANGE		34	/* Math result not representable */
  #define	ENOMSG		35	/* No message of desired type */
  #define	EIDRM		36	/* Identifier removed */
  #define	ECHRNG		37	/* Channel number out of range */
  #define	EL2NSYNC	38	/* Level 2 not synchronized */
  #define	EL3HLT		39	/* Level 3 halted */
  #define	EL3RST		40	/* Level 3 reset */
  #define	ELNRNG		41	/* Link number out of range */
  #define	EUNATCH		42	/* Protocol driver not attached */
  #define	ENOCSI		43	/* No CSI structure available */
  #define	EL2HLT		44	/* Level 2 halted */
  #define	EDEADLK		45	/* Resource deadlock would occur */
  #define	ENOLCK		46	/* No record locks available */
  #define	EBADE		50	/* Invalid exchange */
  #define	EBADR		51	/* Invalid request descriptor */
  #define	EXFULL		52	/* Exchange full */
  #define	ENOANO		53	/* No anode */
  #define	EBADRQC		54	/* Invalid request code */
  #define	EBADSLT		55	/* Invalid slot */
  #define	EDEADLOCK	56	/* File locking deadlock error */
  #define	EBFONT		59	/* Bad font file format */
  #define	ENOSTR		60	/* Device not a stream */
  #define	ENODATA		61	/* No data available */
  #define	ETIME		62	/* Timer expired */
  #define	ENOSR		63	/* Out of streams resources */
  #define	ENONET		64	/* Machine is not on the network */
  #define	ENOPKG		65	/* Package not installed */
  #define	EREMOTE		66	/* Object is remote */
  #define	ENOLINK		67	/* Link has been severed */
  #define	EADV		68	/* Advertise error */
  #define	ESRMNT		69	/* Srmount error */
  #define	ECOMM		70	/* Communication error on send */
  #define	EPROTO		71	/* Protocol error */
  #define	EDOTDOT		73	/* RFS specific error */
  #define	EMULTIHOP	74	/* Multihop attempted */
  #define	EBADMSG		77	/* Not a data message */
  #define	ENAMETOOLONG	78	/* File name too long */
  #define	EOVERFLOW	79	/* Value too large for defined data type */
  #define	ENOTUNIQ	80	/* Name not unique on network */
  #define	EBADFD		81	/* File descriptor in bad state */
  #define	EREMCHG		82	/* Remote address changed */
  #define	ELIBACC		83	/* Can not access a needed shared library */
  #define	ELIBBAD		84	/* Accessing a corrupted shared library */
  #define	ELIBSCN		85	/* .lib section in a.out corrupted */
  #define	ELIBMAX		86	/* Attempting to link in too many shared libraries */
  #define	ELIBEXEC	87	/* Cannot exec a shared library directly */
  #define	EILSEQ		88	/* Illegal byte sequence */
  #define	ENOSYS		89	/* Function not implemented */
  #define	ELOOP		90	/* Too many symbolic links encountered */
  #define	ERESTART	91	/* Interrupted system call should be restarted */
  #define	ESTRPIPE	92	/* Streams pipe error */
  #define	ENOTEMPTY	93	/* Directory not empty */
  #define	EUSERS		94	/* Too many users */
  #define	ENOTSOCK	95	/* Socket operation on non-socket */
  #define	EDESTADDRREQ	96	/* Destination address required */
  #define	EMSGSIZE	97	/* Message too long */
  #define	EPROTOTYPE	98	/* Protocol wrong type for socket */
  #define	ENOPROTOOPT	99	/* Protocol not available */
  #define	EPROTONOSUPPORT	120	/* Protocol not supported */
  #define	ESOCKTNOSUPPORT	121	/* Socket type not supported */
  #define	EOPNOTSUPP	122	/* Operation not supported on transport endpoint */
  #define	EPFNOSUPPORT	123	/* Protocol family not supported */
  #define	EAFNOSUPPORT	124	/* Address family not supported by protocol */
  #define	EADDRINUSE	125	/* Address already in use */
  #define	EADDRNOTAVAIL	126	/* Cannot assign requested address */
  #define	ENETDOWN	127	/* Network is down */
  #define	ENETUNREACH	128	/* Network is unreachable */
  #define	ENETRESET	129	/* Network dropped connection because of reset */
  #define	ECONNABORTED	130	/* Software caused connection abort */
  #define	ECONNRESET	131	/* Connection reset by peer */
  #define	ENOBUFS		132	/* No buffer space available */
  #define	EISCONN		133	/* Transport endpoint is already connected */
  #define	ENOTCONN	134	/* Transport endpoint is not connected */
  #define	EUCLEAN		135	/* Structure needs cleaning */
  #define	ENOTNAM		137	/* Not a XENIX named type file */
  #define	ENAVAIL		138	/* No XENIX semaphores available */
  #define	EISNAM		139	/* Is a named type file */
  #define	EREMOTEIO	140	/* Remote I/O error */
  #define EINIT		141	/* Reserved */
  #define EREMDEV		142	/* Error 142 */
  #define	ESHUTDOWN	143	/* Cannot send after transport endpoint shutdown */
  #define	ETOOMANYREFS	144	/* Too many references: cannot splice */
  #define	ETIMEDOUT	145	/* Connection timed out */
  #define	ECONNREFUSED	146	/* Connection refused */
  #define	EHOSTDOWN	147	/* Host is down */
  #define	EHOSTUNREACH	148	/* No route to host */
  #define	EWOULDBLOCK	EAGAIN	/* Operation would block */
  #define	EALREADY	149	/* Operation already in progress */
  #define	EINPROGRESS	150	/* Operation now in progress */
  #define	ESTALE		151	/* Stale NFS file handle */
  #define ECANCELED	158	/* AIO operation canceled */
  #define	ENOMEDIUM	159	/* No medium found */
  #define	EMEDIUMTYPE	160	/* Wrong medium type */
  #define	EDQUOT		1133	/* Quota exceeded */
  #define ENFSREMOTE	1134	/* ??? */

  #endif /* __ASM_MIPS_ERRNO_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/fcntl.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/fcntl.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: fcntl.h
  ===================================================================
  #ifndef __ASM_MIPS_FCNTL_H
  #define __ASM_MIPS_FCNTL_H

  /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
     located on an ext2 file system */
  #define O_ACCMODE	0x0003
  #define O_RDONLY	0x0000
  #define O_WRONLY	0x0001
  #define O_RDWR		0x0002
  #define O_APPEND	0x0008
  #define O_SYNC		0x0010
  #define O_NONBLOCK	0x0080
  #define O_CREAT         0x0100	/* not fcntl */
  #define O_TRUNC		0x0200	/* not fcntl */
  #define O_EXCL		0x0400	/* not fcntl */
  #define O_NOCTTY	0x0800	/* not fcntl */
  #define FASYNC		0x1000	/* fcntl, for BSD compatibility */

  #define O_NDELAY	O_NONBLOCK

  #define F_DUPFD		0	/* dup */
  #define F_GETFD		1	/* get f_flags */
  #define F_SETFD		2	/* set f_flags */
  #define F_GETFL		3	/* more flags (cloexec) */
  #define F_SETFL		4
  #define F_GETLK		14
  #define F_SETLK		6
  #define F_SETLKW	7

  #define F_SETOWN	24	/*  for sockets. */
  #define F_GETOWN	23	/*  for sockets. */

  /* for F_[GET|SET]FL */
  #define FD_CLOEXEC	1	/* actually anything with low bit set goes */

  /* for posix fcntl() and lockf() */
  #define F_RDLCK		0
  #define F_WRLCK		1
  #define F_UNLCK		2

  /* for old implementation of bsd flock () */
  #define F_EXLCK		4	/* or 3 */
  #define F_SHLCK		8	/* or 4 */

  /* operations for bsd flock(), also used by the kernel implementation */
  #define LOCK_SH		1	/* shared lock */
  #define LOCK_EX		2	/* exclusive lock */
  #define LOCK_NB		4	/* or'd with one of the above to prevent		XXXXXXXXXXXXXXXXXX
  				   blocking */
  #define LOCK_UN		8	/* remove lock */

  typedef struct flock {
  	short l_type;
  	short l_whence;
  	off_t l_start;
  	off_t l_len;
  	long  l_sysid;			/* XXXXXXXXXXXXXXXXXXXXXXXXX */
  	pid_t l_pid;
  	long  pad[4];			/* ZZZZZZZZZZZZZZZZZZZZZZZZZZ */
  } flock_t;

  #endif /* __ASM_MIPS_FCNTL_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/floppy.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/floppy.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: floppy.h
  ===================================================================
  /*
   * Architecture specific parts of the Floppy driver
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1995
   */
  #ifndef __ASM_MIPS_FLOPPY_H
  #define __ASM_MIPS_FLOPPY_H

  #include <asm/bootinfo.h>
  #include <asm/jazz.h>
  #include <asm/jazzdma.h>
  #include <asm/mipsconfig.h>
  #include <asm/vector.h>

  #define fd_inb(port)			feature->fd_inb(port)
  #define fd_outb(value,port)		feature->fd_outb(value,port)

  #define fd_enable_dma()			feature->fd_enable_dma()
  #define fd_disable_dma()		feature->fd_disable_dma()
  #define fd_request_dma()		feature->fd_request_dma()
  #define fd_free_dma()			feature->fd_free_dma()
  #define fd_clear_dma_ff()		feature->fd_clear_dma_ff()
  #define fd_set_dma_mode(mode)		feature->fd_set_dma_mode(mode)
  #define fd_set_dma_addr(addr)		feature->fd_set_dma_addr(addr)
  #define fd_set_dma_count(count)		feature->fd_set_dma_count(count)
  #define fd_get_dma_residue()		feature->fd_get_dma_residue()
  #define fd_enable_irq()			feature->fd_enable_irq()
  #define fd_disable_irq()		feature->fd_disable_irq()
  #define fd_cacheflush(addr, size)	feature->fd_cacheflush((void *)addr, size)
  #define fd_request_irq()        request_irq(FLOPPY_IRQ, floppy_interrupt, \
  					    SA_INTERRUPT|SA_SAMPLE_RANDOM, \
  				            "floppy", NULL)
  #define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);

  #define MAX_BUFFER_SECTORS 24

  static unsigned long mips_dma_mem_alloc(unsigned long size)
  {
  	int order = __get_order(size);
  	unsigned long mem;

  	mem = __get_dma_pages(GFP_KERNEL,order);
  	if(!mem)
  		return 0;
          if (boot_info.machtype == MACH_ACER_PICA_61 ||
              boot_info.machtype == MACH_MIPS_MAGNUM_4000 ||
              boot_info.machtype == MACH_OLIVETTI_M700)
  		vdma_alloc(PHYSADDR(mem), size);
  	return mem;
  }

  static void mips_dma_mem_free(unsigned long addr, unsigned long size)
  {       
          if (boot_info.machtype == MACH_ACER_PICA_61 ||
              boot_info.machtype == MACH_MIPS_MAGNUM_4000 ||
              boot_info.machtype == MACH_OLIVETTI_M700)
  		vdma_free(PHYSADDR(addr));
  	free_pages(addr, __get_order(size));	
  }

  #define fd_dma_mem_alloc(mem,size) mips_dma_mem_alloc(mem,size)
  #define fd_dma_mem_free(mem) mips_dma_mem_free(mem)

  /*
   * And on Mips's the CMOS info fails also ...
   *
   * FIXME: This information should come from the ARC configuration tree
   *        or wherever a particular machine has stored this ...
   */
  #define FLOPPY0_TYPE 4		/* this is wrong for the Olli M700, but who cares... */
  #define FLOPPY1_TYPE 0

  #define FDC1			((boot_info.machtype == MACH_ACER_PICA_61 || \
  				boot_info.machtype == MACH_MIPS_MAGNUM_4000 || \
  				boot_info.machtype == MACH_OLIVETTI_M700) ? \
  				0xe0003000 : 0x3f0)
  static int FDC2=-1;

  #define N_FDC 1			/* do you *really* want a second controller? */
  #define N_DRIVE 8

  /*
   * The DMA channel used by the floppy controller cannot access data at
   * addresses >= 16MB
   *
   * Went back to the 1MB limit, as some people had problems with the floppy
   * driver otherwise. It doesn't matter much for performance anyway, as most
   * floppy accesses go through the track buffer.
   *
   * On MIPSes using vdma, this actually means that *all* transfers go thru
   * the * track buffer since 0x1000000 is always smaller than KSEG0/1.
   * Actually this needs to be a bit more complicated since the so much different
   * hardware available with MIPS CPUs ...
   */
  #define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)

  #endif /* __ASM_MIPS_FLOPPY_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/fpregdef.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/fpregdef.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: fpregdef.h
  ===================================================================
  /*
   * Definitions for the FPU register names
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1995 by Ralf Baechle
   */
  #ifndef __ASM_MIPS_FPREGDEF_H
  #define __ASM_MIPS_FPREGDEF_H

  /*
   * These definitions only cover the R3000-ish 16/32 register model.
   * But we're trying to be R3000 friendly anyway ...
   */
  #define fv0	$f0      /* return value */
  #define fv0f	$f1
  #define fv1	$f2
  #define fv1f	$f3
  #define fa0	$f12     /* argument registers */
  #define fa0f	$f13
  #define fa1	$f14
  #define fa1f	$f15
  #define ft0	$f4      /* caller saved */
  #define ft0f	$f5
  #define ft1	$f6
  #define ft1f	$f7
  #define ft2	$f8
  #define ft2f	$f9
  #define ft3	$f10
  #define ft3f	$f11
  #define ft4	$f16
  #define ft4f	$f17
  #define ft5	$f18
  #define ft5f	$f19
  #define fs0	$f20     /* callee saved */
  #define fs0f	$f21
  #define fs1	$f22
  #define fs1f	$f23
  #define fs2	$f24
  #define fs2f	$f25
  #define fs3	$f26
  #define fs3f	$f27
  #define fs4	$f28
  #define fs4f	$f29
  #define fs5	$f30
  #define fs5f	$f31

  #define fcr31	$31      /* FPU status register */

  #endif /* !defined (__ASM_MIPS_FPREGDEF_H) */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/gdb-stub.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/gdb-stub.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: gdb-stub.h
  ===================================================================
  /*
   *  include/asm-mips/gdb-stub.h
   *
   *  Copyright (C) 1995 Andreas Busse
   */

  #ifndef __ASM_MIPS_GDB_STUB_H
  #define __ASM_MIPS_GDB_STUB_H

  /*
   * important register numbers
   */

  #define REG_EPC			37
  #define REG_FP			72
  #define REG_SP			29

  /*
   * Stack layout for the GDB exception handler
   * Derived from the stack layout described in asm-mips/stackframe.h
   *
   * The first PTRSIZE*5 bytes are argument save space for C subroutines.
   */
  #define NUMREGS			90

  #define GDB_FR_REG0		(PTRSIZE*5)			/* 0 */
  #define GDB_FR_REG1		((GDB_FR_REG0) + 4)		/* 1 */
  #define GDB_FR_REG2		((GDB_FR_REG1) + 4)		/* 2 */
  #define GDB_FR_REG3		((GDB_FR_REG2) + 4)		/* 3 */
  #define GDB_FR_REG4		((GDB_FR_REG3) + 4)		/* 4 */
  #define GDB_FR_REG5		((GDB_FR_REG4) + 4)		/* 5 */
  #define GDB_FR_REG6		((GDB_FR_REG5) + 4)		/* 6 */
  #define GDB_FR_REG7		((GDB_FR_REG6) + 4)		/* 7 */
  #define GDB_FR_REG8		((GDB_FR_REG7) + 4)		/* 8 */
  #define GDB_FR_REG9	        ((GDB_FR_REG8) + 4)		/* 9 */
  #define GDB_FR_REG10		((GDB_FR_REG9) + 4)		/* 10 */
  #define GDB_FR_REG11		((GDB_FR_REG10) + 4)		/* 11 */
  #define GDB_FR_REG12		((GDB_FR_REG11) + 4)		/* 12 */
  #define GDB_FR_REG13		((GDB_FR_REG12) + 4)		/* 13 */
  #define GDB_FR_REG14		((GDB_FR_REG13) + 4)		/* 14 */
  #define GDB_FR_REG15		((GDB_FR_REG14) + 4)		/* 15 */
  #define GDB_FR_REG16		((GDB_FR_REG15) + 4)		/* 16 */
  #define GDB_FR_REG17		((GDB_FR_REG16) + 4)		/* 17 */
  #define GDB_FR_REG18		((GDB_FR_REG17) + 4)		/* 18 */
  #define GDB_FR_REG19		((GDB_FR_REG18) + 4)		/* 19 */
  #define GDB_FR_REG20		((GDB_FR_REG19) + 4)		/* 20 */
  #define GDB_FR_REG21		((GDB_FR_REG20) + 4)		/* 21 */
  #define GDB_FR_REG22		((GDB_FR_REG21) + 4)		/* 22 */
  #define GDB_FR_REG23		((GDB_FR_REG22) + 4)		/* 23 */
  #define GDB_FR_REG24		((GDB_FR_REG23) + 4)		/* 24 */
  #define GDB_FR_REG25		((GDB_FR_REG24) + 4)		/* 25 */
  #define GDB_FR_REG26		((GDB_FR_REG25) + 4)		/* 26 */
  #define GDB_FR_REG27		((GDB_FR_REG26) + 4)		/* 27 */
  #define GDB_FR_REG28		((GDB_FR_REG27) + 4)		/* 28 */
  #define GDB_FR_REG29		((GDB_FR_REG28) + 4)		/* 29 */
  #define GDB_FR_REG30		((GDB_FR_REG29) + 4)		/* 30 */
  #define GDB_FR_REG31		((GDB_FR_REG30) + 4)		/* 31 */

  /*
   * Saved special registers
   */
  #define GDB_FR_STATUS		((GDB_FR_REG31) + 4)		/* 32 */
  #define GDB_FR_LO		((GDB_FR_STATUS) + 4)		/* 33 */
  #define GDB_FR_HI		((GDB_FR_LO) + 4)		/* 34 */
  #define GDB_FR_BADVADDR		((GDB_FR_HI) + 4)		/* 35 */
  #define GDB_FR_CAUSE		((GDB_FR_BADVADDR) + 4)		/* 36 */
  #define GDB_FR_EPC		((GDB_FR_CAUSE) + 4)		/* 37 */

  /*
   * Saved floating point registers
   */
  #define GDB_FR_FPR0		((GDB_FR_EPC) + 4)		/* 38 */
  #define GDB_FR_FPR1		((GDB_FR_FPR0) + 4)		/* 39 */
  #define GDB_FR_FPR2		((GDB_FR_FPR1) + 4)		/* 40 */
  #define GDB_FR_FPR3		((GDB_FR_FPR2) + 4)		/* 41 */
  #define GDB_FR_FPR4		((GDB_FR_FPR3) + 4)		/* 42 */
  #define GDB_FR_FPR5		((GDB_FR_FPR4) + 4)		/* 43 */
  #define GDB_FR_FPR6		((GDB_FR_FPR5) + 4)		/* 44 */
  #define GDB_FR_FPR7		((GDB_FR_FPR6) + 4)		/* 45 */
  #define GDB_FR_FPR8		((GDB_FR_FPR7) + 4)		/* 46 */
  #define GDB_FR_FPR9		((GDB_FR_FPR8) + 4)		/* 47 */
  #define GDB_FR_FPR10		((GDB_FR_FPR9) + 4)		/* 48 */
  #define GDB_FR_FPR11		((GDB_FR_FPR10) + 4)		/* 49 */
  #define GDB_FR_FPR12		((GDB_FR_FPR11) + 4)		/* 50 */
  #define GDB_FR_FPR13		((GDB_FR_FPR12) + 4)		/* 51 */
  #define GDB_FR_FPR14		((GDB_FR_FPR13) + 4)		/* 52 */
  #define GDB_FR_FPR15		((GDB_FR_FPR14) + 4)		/* 53 */
  #define GDB_FR_FPR16		((GDB_FR_FPR15) + 4)		/* 54 */
  #define GDB_FR_FPR17		((GDB_FR_FPR16) + 4)		/* 55 */
  #define GDB_FR_FPR18		((GDB_FR_FPR17) + 4)		/* 56 */
  #define GDB_FR_FPR19		((GDB_FR_FPR18) + 4)		/* 57 */
  #define GDB_FR_FPR20		((GDB_FR_FPR19) + 4)		/* 58 */
  #define GDB_FR_FPR21		((GDB_FR_FPR20) + 4)		/* 59 */
  #define GDB_FR_FPR22		((GDB_FR_FPR21) + 4)		/* 60 */
  #define GDB_FR_FPR23		((GDB_FR_FPR22) + 4)		/* 61 */
  #define GDB_FR_FPR24		((GDB_FR_FPR23) + 4)		/* 62 */
  #define GDB_FR_FPR25		((GDB_FR_FPR24) + 4)		/* 63 */
  #define GDB_FR_FPR26		((GDB_FR_FPR25) + 4)		/* 64 */
  #define GDB_FR_FPR27		((GDB_FR_FPR26) + 4)		/* 65 */
  #define GDB_FR_FPR28		((GDB_FR_FPR27) + 4)		/* 66 */
  #define GDB_FR_FPR29		((GDB_FR_FPR28) + 4)		/* 67 */
  #define GDB_FR_FPR30		((GDB_FR_FPR29) + 4)		/* 68 */
  #define GDB_FR_FPR31		((GDB_FR_FPR30) + 4)		/* 69 */

  #define GDB_FR_FSR		((GDB_FR_FPR31) + 4)		/* 70 */
  #define GDB_FR_FIR		((GDB_FR_FSR) + 4)		/* 71 */
  #define GDB_FR_FRP		((GDB_FR_FIR) + 4)		/* 72 */

  #define GDB_FR_DUMMY		((GDB_FR_FRP) + 4)		/* 73, unused ??? */

  /*
   * Again, CP0 registers
   */
  #define GDB_FR_CP0_INDEX	((GDB_FR_DUMMY) + 4)		/* 74 */
  #define GDB_FR_CP0_RANDOM	((GDB_FR_CP0_INDEX) + 4)	/* 75 */
  #define GDB_FR_CP0_ENTRYLO0	((GDB_FR_CP0_RANDOM) + 4)	/* 76 */
  #define GDB_FR_CP0_ENTRYLO1	((GDB_FR_CP0_ENTRYLO0) + 4)	/* 77 */
  #define GDB_FR_CP0_REG4		((GDB_FR_CP0_ENTRYLO1) + 4)	/* 78 */
  #define GDB_FR_CP0_PAGEMASK	((GDB_FR_CP0_REG4) + 4)		/* 79 */
  #define GDB_FR_CP0_WIRED	((GDB_FR_CP0_PAGEMASK) + 4)	/* 80 */
  #define GDB_FR_CP0_REG7		((GDB_FR_CP0_WIRED) + 4)	/* 81 */
  #define GDB_FR_CP0_REG8		((GDB_FR_CP0_REG7) + 4)		/* 82 */
  #define GDB_FR_CP0_REG9		((GDB_FR_CP0_REG8) + 4)		/* 83 */
  #define GDB_FR_CP0_ENTRYHI	((GDB_FR_CP0_REG9) + 4)		/* 84 */
  #define GDB_FR_CP0_REG11	((GDB_FR_CP0_ENTRYHI) + 4)	/* 85 */
  #define GDB_FR_CP0_REG12	((GDB_FR_CP0_REG11) + 4)	/* 86 */
  #define GDB_FR_CP0_REG13	((GDB_FR_CP0_REG12) + 4)	/* 87 */
  #define GDB_FR_CP0_REG14	((GDB_FR_CP0_REG13) + 4)	/* 88 */
  #define GDB_FR_CP0_PRID		((GDB_FR_CP0_REG14) + 4)	/* 89 */

  #define GDB_FR_SIZE		((((GDB_FR_CP0_PRID) + 4) + (PTRSIZE-1)) & ~(PTRSIZE-1))

  #ifndef __LANGUAGE_ASSEMBLY__

  /*
   * This is the same as above, but for the high-level
   * part of the GDB stub.
   */

  struct gdb_regs {
  	/*
  	 * Pad bytes for argument save space on the stack
  	 * 20/40 Bytes for 32/64 bit code
  	 */
  	unsigned long pad0[5];

  	/*
  	 * saved main processor registers
  	 */
  	long	 reg0,  reg1,  reg2,  reg3,  reg4,  reg5,  reg6,  reg7;
  	long	 reg8,  reg9, reg10, reg11, reg12, reg13, reg14, reg15;
  	long	reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
  	long	reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;

  	/*
  	 * Saved special registers
  	 */
  	long	cp0_status;
  	long	lo;
  	long	hi;
  	long	cp0_badvaddr;
  	long	cp0_cause;
  	long	cp0_epc;

  	/*
  	 * Saved floating point registers
  	 */
  	long	fpr0,  fpr1,  fpr2,  fpr3,  fpr4,  fpr5,  fpr6,  fpr7;
  	long	fpr8,  fpr9,  fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
  	long	fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
  	long	fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;

  	long	cp1_fsr;
  	long	cp1_fir;

  	/*
  	 * Frame pointer
  	 */
  	long	frame_ptr;
  	long    dummy;		/* unused */

  	/*
  	 * saved cp0 registers
  	 */
  	long	cp0_index;
  	long	cp0_random;
  	long	cp0_entrylo0;
  	long	cp0_entrylo1;
  	long	cp0_reg4;
  	long	cp0_pagemask;
  	long	cp0_wired;
  	long	cp0_reg7;
  	long	cp0_reg8;
  	long	cp0_reg9;
  	long	cp0_entryhi;
  	long	cp0_reg11;
  	long	cp0_reg12;
  	long	cp0_reg13;
  	long	cp0_reg14;
  	long	cp0_prid;
  };

  /*
   * Prototypes
   */

  void set_debug_traps(void);

  #endif /* __LANGUAGE_ASSEMBLY */
  #endif /* __ASM_MIPS_GDB_STUB_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/io.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/io.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: io.h
  ===================================================================
  #ifndef __ASM_MIPS_IO_H
  #define __ASM_MIPS_IO_H

  #include <asm/mipsconfig.h>
  #include <asm/segment.h>

  /*
   * This file contains the definitions for the MIPS counterpart of the
   * x86 in/out instructions. This heap of macros and C results in much
   * better code than the approach of doing it in plain C, though that's
   * probably not needed.
   *
   *   Ralf
   *
   * This file contains the definitions for the x86 IO instructions
   * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   * versions of the single-IO instructions (inb_p/inw_p/..).
   *
   * This file is not meant to be obfuscating: it's just complicated
   * to (a) handle it all in a way that makes gcc able to optimize it
   * as well as possible and (b) trying to avoid writing the same thing
   * over and over again with slight variations and possibly making a
   * mistake somewhere.
   */

  /*
   * Thanks to James van Artsdalen for a better timing-fix than
   * the two short jumps: using outb's to a nonexistent port seems
   * to guarantee better timings even on fast machines.
   *
   * On the other hand, I'd like to be sure of a non-existent port:
   * I feel a bit unsafe about using 0x80 (should be safe, though)
   *
   *		Linus
   */

  #define __SLOW_DOWN_IO \
  	__asm__ __volatile__( \
  		"sb\t$0,0x80(%0)" \
  		: : "r" (PORT_BASE));

  #ifdef REALLY_SLOW_IO
  #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
  #else
  #define SLOW_DOWN_IO __SLOW_DOWN_IO
  #endif

  /*
   * Change virtual addresses to physical addresses and vv.
   * These are trivial on the 1:1 Linux/MIPS mapping
   */
  extern inline unsigned long virt_to_phys(volatile void * address)
  {
  	return (unsigned long) address - KSEG0;
  }

  extern inline void * phys_to_virt(unsigned long address)
  {
  	return (void *) address + KSEG0;
  }

  /*
   * IO bus memory addresses are also 1:1 with the physical address
   * FIXME: This assumption is wrong for the Deskstation Tyne
   */
  #define virt_to_bus virt_to_phys
  #define bus_to_virt phys_to_virt

  /*
   * readX/writeX() are used to access memory mapped devices. On some
   * architectures the memory mapped IO stuff needs to be accessed
   * differently. On the x86 architecture, we just read/write the
   * memory location directly.
   */
  #define readb(addr) (*(volatile unsigned char *) (addr))
  #define readw(addr) (*(volatile unsigned short *) (addr))
  #define readl(addr) (*(volatile unsigned int *) (addr))

  #define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
  #define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
  #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))

  #define memset_io(a,b,c)	memset((void *)(a),(b),(c))
  #define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
  #define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))

  /*
   * Again, MIPS does not require mem IO specific function.
   */

  #define eth_io_copy_and_sum(a,b,c,d)	eth_copy_and_sum((a),(void *)(b),(c),(d))

  /*
   * Talk about misusing macros..
   */

  #define __OUT1(s) \
  extern inline void __out##s(unsigned int value, unsigned int port) {

  #define __OUT2(m) \
  __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"

  #define __OUT(m,s) \
  __OUT1(s) __OUT2(m) : : "r" (value), "i" (0), "r" (PORT_BASE+port)); } \
  __OUT1(s##c) __OUT2(m) : : "r" (value), "ir" (port), "r" (PORT_BASE)); } \
  __OUT1(s##_p) __OUT2(m) : : "r" (value), "i" (0), "r" (PORT_BASE+port)); \
  	SLOW_DOWN_IO; } \
  __OUT1(s##c_p) __OUT2(m) : : "r" (value), "ir" (port), "r" (PORT_BASE)); \
  	SLOW_DOWN_IO; }

  #define __IN1(t,s) \
  extern __inline__ t __in##s(unsigned int port) { t _v;

  /*
   * Useless nops will be removed by the assembler
   */
  #define __IN2(m) \
  __asm__ __volatile__ ("l" #m "u\t%0,%1(%2)\n\tnop"

  #define __IN(t,m,s) \
  __IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); return _v; } \
  __IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (PORT_BASE)); return _v; } \
  __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); SLOW_DOWN_IO; return _v; } \
  __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (PORT_BASE)); SLOW_DOWN_IO; return _v; }

  #define __INS1(s) \
  extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {

  #define __INS2(m) \
  __asm__ __volatile__ ( \
  	".set\tnoreorder\n\t" \
  	".set\tnoat\n" \
  	"1:\tl" #m "u\t$1,%4(%5)\n\t" \
  	"subu\t%1,1\n\t" \
  	"s" #m "\t$1,(%0)\n\t" \
  	"bne\t$0,%1,1b\n\t" \
  	"addiu\t%0,%6\n\t" \
  	".set\tat\n\t" \
  	".set\treorder"

  #define __INS(m,s,i) \
  __INS1(s) __INS2(m) \
  	: "=r" (addr), "=r" (count) \
  	: "0" (addr), "1" (count), "i" (0), "r" (PORT_BASE+port), "I" (i) \
  	: "$1");} \
  __INS1(s##c) __INS2(m) \
  	: "=r" (addr), "=r" (count) \
  	: "0" (addr), "1" (count), "ir" (port), "r" (PORT_BASE), "I" (i) \
  	: "$1");}

  #define __OUTS1(s) \
  extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {

  #define __OUTS2(m) \
  __asm__ __volatile__ ( \
          ".set\tnoreorder\n\t" \
          ".set\tnoat\n" \
          "1:\tl" #m "u\t$1,(%0)\n\t" \
          "subu\t%1,%1,1\n\t" \
          "s" #m "\t$1,%4(%5)\n\t" \
          "bne\t$0,%1,1b\n\t" \
          "addiu\t%0,%0,%6\n\t" \
          ".set\tat\n\t" \
          ".set\treorder"

  #define __OUTS(m,s,i) \
  __OUTS1(s) __OUTS2(m) \
  	: "=r" (addr), "=r" (count) \
  	: "0" (addr), "1" (count), "i" (0), "r" (PORT_BASE+port), "I" (i) \
  	: "$1");} \
  __OUTS1(s##c) __OUTS2(m) \
  	: "=r" (addr), "=r" (count) \
  	: "0" (addr), "1" (count), "ir" (port), "r" (PORT_BASE), "I" (i) \
  	: "$1");}

  __IN(unsigned char,b,b)
  __IN(unsigned short,h,w)
  __IN(unsigned int,w,l)

  __OUT(b,b)
  __OUT(h,w)
  __OUT(w,l)

  __INS(b,b,1)
  __INS(h,w,2)
  __INS(w,l,4)

  __OUTS(b,b,1)
  __OUTS(h,w,2)
  __OUTS(w,l,4)

  /*
   * Note that due to the way __builtin_constant_p() works, you
   *  - can't use it inside a inline function (it will never be true)
   *  - you don't have to worry about side effects within the __builtin..
   */
  #define outb(val,port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outbc((val),(port)) : \
  	__outb((val),(port)))

  #define inb(port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inbc(port) : \
  	__inb(port))

  #define outb_p(val,port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outbc_p((val),(port)) : \
  	__outb_p((val),(port)))

  #define inb_p(port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inbc_p(port) : \
  	__inb_p(port))

  #define outw(val,port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outwc((val),(port)) : \
  	__outw((val),(port)))

  #define inw(port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inwc(port) : \
  	__inw(port))

  #define outw_p(val,port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outwc_p((val),(port)) : \
  	__outw_p((val),(port)))

  #define inw_p(port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inwc_p(port) : \
  	__inw_p(port))

  #define outl(val,port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outlc((val),(port)) : \
  	__outl((val),(port)))

  #define inl(port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inlc(port) : \
  	__inl(port))

  #define outl_p(val,port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outlc_p((val),(port)) : \
  	__outl_p((val),(port)))

  #define inl_p(port) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inlc_p(port) : \
  	__inl_p(port))

  #define outsb(port,addr,count) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outsbc((port),(addr),(count)) : \
  	__outsb ((port),(addr),(count)))

  #define insb(port,addr,count) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__insbc((port),(addr),(count)) : \
  	__insb((port),(addr),(count)))

  #define outsw(port,addr,count) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outswc((port),(addr),(count)) : \
  	__outsw ((port),(addr),(count)))

  #define insw(port,addr,count) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inswc((port),(addr),(count)) : \
  	__insw((port),(addr),(count)))

  #define outsl(port,addr,count) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__outslc((port),(addr),(count)) : \
  	__outsl ((port),(addr),(count)))

  #define insl(port,addr,count) \
  ((__builtin_constant_p((port)) && (port) < 32768) ? \
  	__inslc((port),(addr),(count)) : \
  	__insl((port),(addr),(count)))

  #endif /* __ASM_MIPS_IO_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/ioctl.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/ioctl.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: ioctl.h
  ===================================================================
  #ifndef __ASM_MIPS_IOCTL_H
  #define __ASM_MIPS_IOCTL_H

  /*
   * The original linux ioctl numbering scheme was just a general
   * "anything goes" setup, where more or less random numbers were
   * assigned.  Sorry, I was clueless when I started out on this.
   *
   * On the alpha, we'll try to clean it up a bit, using a more sane
   * ioctl numbering, and also trying to be compatible with OSF/1 in
   * the process. I'd like to clean it up for the i386 as well, but
   * it's so painful recognizing both the new and the old numbers..
   *
   * The same applies for the MIPS ABI; in fact even the macros
   * from Linux/Alpha fit almost perfectly.
   */

  #define _IOC_NRBITS	8
  #define _IOC_TYPEBITS	8
  #define _IOC_SIZEBITS	13
  #define _IOC_DIRBITS	3

  #define _IOC_NRMASK	((1 << _IOC_NRBITS)-1)
  #define _IOC_TYPEMASK	((1 << _IOC_TYPEBITS)-1)
  #define _IOC_SIZEMASK	((1 << _IOC_SIZEBITS)-1)
  #define _IOC_DIRMASK	((1 << _IOC_DIRBITS)-1)

  #define _IOC_NRSHIFT	0
  #define _IOC_TYPESHIFT	(_IOC_NRSHIFT+_IOC_NRBITS)
  #define _IOC_SIZESHIFT	(_IOC_TYPESHIFT+_IOC_TYPEBITS)
  #define _IOC_DIRSHIFT	(_IOC_SIZESHIFT+_IOC_SIZEBITS)

  /*
   * We to additionally limit parameters to a maximum 255 bytes.
   */
  #define _IOC_SLMASK	0xff

  /*
   * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
   * And this turns out useful to catch old ioctl numbers in header
   * files for us.
   */
  #define _IOC_NONE	1U
  #define _IOC_READ	2U
  #define _IOC_WRITE	4U

  /*
   * The following are included for compatibility
   */
  #define _IOC_VOID	0x20000000
  #define _IOC_OUT	0x40000000
  #define _IOC_IN		0x80000000
  #define _IOC_INOUT	(IOC_IN|IOC_OUT)

  #define _IOC(dir,type,nr,size) \
  	(((dir)  << _IOC_DIRSHIFT) | \
  	 ((type) << _IOC_TYPESHIFT) | \
  	 ((nr)   << _IOC_NRSHIFT) | \
  	 (((size) & _IOC_SLMASK) << _IOC_SIZESHIFT))

  /* used to create numbers */
  #define _IO(type,nr)		_IOC(_IOC_NONE,(type),(nr),0)
  #define _IOR(type,nr,size)	_IOC(_IOC_READ,(type),(nr),sizeof(size))
  #define _IOW(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),sizeof(size))
  #define _IOWR(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))

  /* used to decode them.. */
  #define _IOC_DIR(nr)		(((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
  #define _IOC_TYPE(nr)		(((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
  #define _IOC_NR(nr)		(((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
  #define _IOC_SIZE(nr)		(((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)

  /* ...and for the drivers/sound files... */

  #define IOC_IN		(_IOC_WRITE << _IOC_DIRSHIFT)
  #define IOC_OUT		(_IOC_READ << _IOC_DIRSHIFT)
  #define IOC_INOUT	((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
  #define IOCSIZE_MASK	(_IOC_SIZEMASK << _IOC_SIZESHIFT)
  #define IOCSIZE_SHIFT	(_IOC_SIZESHIFT)

  #endif /* __ASM_MIPS_IOCTL_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/ioctls.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/ioctls.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: ioctls.h
  ===================================================================
  #ifndef __ASM_MIPS_IOCTLS_H
  #define __ASM_MIPS_IOCTLS_H

  #include <asm/ioctl.h>

  #define TCGETA		0x5401
  #define TCSETA		0x5402
  #define TCSETAW		0x5403
  #define TCSETAF		0x5404

  #define TCSBRK		0x5405
  #define TCXONC		0x5406
  #define TCFLSH		0x5407

  #define TCGETS		0x540d
  #define TCSETS		0x540e
  #define TCSETSW		0x540f
  #define TCSETSF		0x5410

  #define TIOCEXCL	0x740d		/* set exclusive use of tty */
  #define TIOCNXCL	0x740e		/* reset exclusive use of tty */
  #define TIOCOUTQ	0x7472		/* output queue size */
  #define TIOCSTI		0x5472		/* simulate terminal input */
  #define TIOCMGET	0x741d		/* get all modem bits */
  #define TIOCMBIS	0x741b		/* bis modem bits */
  #define TIOCMBIC	0x741c		/* bic modem bits */
  #define TIOCMSET	0x741a		/* set all modem bits */
  #define TIOCPKT		0x5470		/* pty: set/clear packet mode */
  #define		TIOCPKT_DATA		0x00	/* data packet */
  #define		TIOCPKT_FLUSHREAD	0x01	/* flush packet */
  #define		TIOCPKT_FLUSHWRITE	0x02	/* flush packet */
  #define		TIOCPKT_STOP		0x04	/* stop output */
  #define		TIOCPKT_START		0x08	/* start output */
  #define		TIOCPKT_NOSTOP		0x10	/* no more ^S, ^Q */
  #define		TIOCPKT_DOSTOP		0x20	/* now do ^S ^Q */
  #if 0
  #define		TIOCPKT_IOCTL		0x40	/* state change of pty driver */
  #endif
  #define TIOCSWINSZ	_IOW('t', 103, struct winsize)	/* set window size */
  #define TIOCGWINSZ	_IOR('t', 104, struct winsize)	/* get window size */
  #define TIOCNOTTY	0x5471		/* void tty association */
  #define TIOCSETD	0x7401
  #define TIOCGETD	0x7400

  #define FIOCLEX		0x6601
  #define FIONCLEX	0x6602		/* these numbers need to be adjusted. */
  #define FIOASYNC	0x667d
  #define FIONBIO		0x667e

  						/* 116-117 compat */
  #define TIOCSPGRP	_IOW('t', 118, int)	/* set pgrp of tty */
  #define TIOCGPGRP	_IOR('t', 119, int)	/* get pgrp of tty */
  #define TIOCCONS	_IOW('t', 120, int)	/* become virtual console */

  #define FIONREAD	0x467f
  #define TIOCINQ		FIONREAD

  #if 0
  #define	TIOCSETA	_IOW('t', 20, struct termios) /* set termios struct */
  #define	TIOCSETAW	_IOW('t', 21, struct termios) /* drain output, set */
  #define	TIOCSETAF	_IOW('t', 22, struct termios) /* drn out, fls in, set */
  #define	TIOCGETD	_IOR('t', 26, int)	/* get line discipline */
  #define	TIOCSETD	_IOW('t', 27, int)	/* set line discipline */
  						/* 127-124 compat */
  #endif

  /* I hope the range from 0x5480 on is free ... */
  #define TIOCSCTTY	0x5480		/* become controlling tty */
  #define TIOCGSOFTCAR	0x5481
  #define TIOCSSOFTCAR	0x5482
  #define TIOCLINUX	0x5483
  #define TIOCGSERIAL	0x5484
  #define TIOCSSERIAL	0x5485

  #define TCSBRKP		0x5486	/* Needed for POSIX tcsendbreak() */
  #define TIOCTTYGSTRUCT	0x5487  /* For debugging only */

  #define TIOCSERCONFIG	0x5488
  #define TIOCSERGWILD	0x5489
  #define TIOCSERSWILD	0x548a
  #define TIOCGLCKTRMIOS	0x548b
  #define TIOCSLCKTRMIOS	0x548c
  #define TIOCSERGSTRUCT	0x548d /* For debugging only */
  #define TIOCSERGETLSR   0x548e /* Get line status register */
  #define TIOCSERGETMULTI 0x548f /* Get multiport config  */
  #define TIOCSERSETMULTI 0x5490 /* Set multiport config */

  /* ----------------------------------------------------------------------- */

  /* c_cc characters */
  #define VINTR		 0		/* Interrupt character [ISIG].  */
  #define VQUIT		 1		/* Quit character [ISIG].  */
  #define VERASE		 2		/* Erase character [ICANON].  */
  #define VKILL		 3		/* Kill-line character [ICANON].  */
  #define VEOF		 4		/* End-of-file character [ICANON].  */
  #define VMIN		VEOF		/* Minimum number of bytes read at once [!ICANON].  */
  #define VEOL		 5		/* End-of-line character [ICANON].  */
  #define VTIME		VEOL		/* Time-out value (tenths of a second) [!ICANON].  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define VEOL2		 6		/* Second EOL character [ICANON].  */
  /* The next two are guesses ... */
  #define VSWTC		 7		/* ??? */
  #endif
  #define VSWTCH		VSWTC
  #define VSTART		 8		/* Start (X-ON) character [IXON, IXOFF].  */
  #define VSTOP		 9		/* Stop (X-OFF) character [IXON, IXOFF].  */
  #define VSUSP		10		/* Suspend character [ISIG].  */
  #if 0
  /*
   * VDSUSP is not supported
   */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define VDSUSP		11		/* Delayed suspend character [ISIG].  */
  #endif
  #endif
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define VREPRINT	12		/* Reprint-line character [ICANON].  */
  #endif
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define VDISCARD	13		/* Discard character [IEXTEN].  */
  #define VWERASE		14		/* Word-erase character [ICANON].  */
  #define VLNEXT		15		/* Literal-next character [IEXTEN].  */
  #endif
  /*
   * 17 - 19 are reserved
   */

  #ifdef __KERNEL__
  /*
   *	intr=^C		quit=^|		erase=del	kill=^U
   *	eof=^D		eol=time=\0	eol2=\0		swtc=\0
   *	start=^Q	stop=^S		susp=^Z		vdsusp=
   *	reprint=^R	discard=^U	werase=^W	lnext=^V
   */
  #define INIT_C_CC "\003\034\177\025\004\0\0\0\021\023\032\0\022\017\027\026"
  #endif

  /* c_iflag bits */
  #define IGNBRK	0000001		/* Ignore break condition.  */
  #define BRKINT	0000002		/* Signal interrupt on break.  */
  #define IGNPAR	0000004		/* Ignore characters with parity errors.  */
  #define PARMRK	0000010		/* Mark parity and framing errors.  */
  #define INPCK	0000020		/* Enable input parity check.  */
  #define ISTRIP	0000040		/* Strip 8th bit off characters.  */
  #define INLCR	0000100		/* Map NL to CR on input.  */
  #define IGNCR	0000200		/* Ignore CR.  */
  #define ICRNL	0000400		/* Map CR to NL on input.  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define IUCLC	0001000		/* Map upper case to lower case on input.  */
  #endif
  #define IXON	0002000		/* Enable start/stop output control.  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define IXANY	0004000		/* Any character will restart after stop.  */
  #endif
  #define IXOFF	0010000		/* Enable start/stop input control.  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define IMAXBEL	0020000		/* Ring bell when input queue is full.  */
  #endif

  /* c_oflag bits */
  #define OPOST	0000001		/* Perform output processing.  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define OLCUC	0000002		/* Map lower case to upper case on output.  */
  #define ONLCR	0000004		/* Map NL to CR-NL on output.  */
  #define OCRNL	0000010
  #define ONOCR	0000020
  #define ONLRET	0000040
  #define OFILL	0000100
  #define OFDEL	0000200
  #define NLDLY	0000400
  #define   NL0	0000000
  #define   NL1	0000400
  #define CRDLY	0003000
  #define   CR0	0000000
  #define   CR1	0001000
  #define   CR2	0002000
  #define   CR3	0003000
  #define TABDLY	0014000
  #define   TAB0	0000000
  #define   TAB1	0004000
  #define   TAB2	0010000
  #define   TAB3	0014000
  #define   XTABS	0014000
  #define BSDLY	0020000
  #define   BS0	0000000
  #define   BS1	0020000
  #define VTDLY	0040000
  #define   VT0	0000000
  #define   VT1	0040000
  #define FFDLY	0100000
  #define   FF0	0000000
  #define   FF1	0100000
  /*
  #define PAGEOUT ???
  #define WRAP    ???
   */
  #endif

  /* c_cflag bit meaning */
  #define CBAUD	0010017
  #define  B0	0000000		/* hang up */
  #define  B50	0000001
  #define  B75	0000002
  #define  B110	0000003
  #define  B134	0000004
  #define  B150	0000005
  #define  B200	0000006
  #define  B300	0000007
  #define  B600	0000010
  #define  B1200	0000011
  #define  B1800	0000012
  #define  B2400	0000013
  #define  B4800	0000014
  #define  B9600	0000015
  #define  B19200	0000016
  #define  B38400	0000017
  #define EXTA B19200
  #define EXTB B38400
  #define CSIZE	0000060		/* Number of bits per byte (mask).  */
  #define   CS5	0000000		/* 5 bits per byte.  */
  #define   CS6	0000020		/* 6 bits per byte.  */
  #define   CS7	0000040		/* 7 bits per byte.  */
  #define   CS8	0000060		/* 8 bits per byte.  */
  #define CSTOPB	0000100		/* Two stop bits instead of one.  */
  #define CREAD	0000200		/* Enable receiver.  */
  #define PARENB	0000400		/* Parity enable.  */
  #define PARODD	0001000		/* Odd parity instead of even.  */
  #define HUPCL	0002000		/* Hang up on last close.  */
  #define CLOCAL	0004000		/* Ignore modem status lines.  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define CBAUDEX 0010000
  #define  B57600  0010001
  #define  B115200 0010002
  #define  B230400 0010003
  #define  B460800 0010004
  #define CIBAUD	  002003600000	/* input baud rate (not used) */
  #define CRTSCTS	  020000000000		/* flow control */
  #endif

  /* c_lflag bits */
  #define ISIG	0000001		/* Enable signals.  */
  #define ICANON	0000002		/* Do erase and kill processing.  */
  #define XCASE	0000004
  #define ECHO	0000010		/* Enable echo.  */
  #define ECHOE	0000020		/* Visual erase for ERASE.  */
  #define ECHOK	0000040		/* Echo NL after KILL.  */
  #define ECHONL	0000100		/* Echo NL even if ECHO is off.  */
  #define NOFLSH	0000200		/* Disable flush after interrupt.  */
  #define IEXTEN	0000400		/* Enable DISCARD and LNEXT.  */
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define ECHOCTL	0001000		/* Echo control characters as ^X.  */
  #define ECHOPRT	0002000		/* Hardcopy visual erase.  */
  #define ECHOKE	0004000		/* Visual erase for KILL.  */
  #endif
  #define FLUSHO	0020000
  #if defined (__USE_BSD) || defined (__KERNEL__)
  #define PENDIN	0040000		/* Retype pending input (state).  */
  #endif
  #define TOSTOP	0100000		/* Send SIGTTOU for background output.  */
  #define ITOSTOP	TOSTOP

  /* modem lines */
  #define TIOCM_LE	0x001		/* line enable */
  #define TIOCM_DTR	0x002		/* data terminal ready */
  #define TIOCM_RTS	0x004		/* request to send */
  #define TIOCM_ST	0x010		/* secondary transmit */
  #define TIOCM_SR	0x020		/* secondary receive */
  #define TIOCM_CTS	0x040		/* clear to send */
  #define TIOCM_CAR	0x100		/* carrier detect */
  #define TIOCM_CD	TIOCM_CAR
  #define TIOCM_RNG	0x200		/* ring */
  #define TIOCM_RI	TIOCM_RNG
  #define TIOCM_DSR	0x400		/* data set ready */

  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
  #define TIOCSER_TEMT    0x01	/* Transmitter physically empty */

  /* tcflow() and TCXONC use these */
  #define	TCOOFF		0	/* Suspend output.  */
  #define	TCOON		1	/* Restart suspended output.  */
  #define	TCIOFF		2	/* Send a STOP character.  */
  #define	TCION		3	/* Send a START character.  */

  /* tcflush() and TCFLSH use these */
  #define	TCIFLUSH	0	/* Discard data received but not yet read.  */
  #define	TCOFLUSH	1	/* Discard data written but not yet sent.  */
  #define	TCIOFLUSH	2	/* Discard all pending data.  */

  /* tcsetattr uses these */
  #define	TCSANOW		TCSETS	/* Change immediately.  */
  #define	TCSADRAIN	TCSETSW	/* Change when pending output is written.  */
  #define	TCSAFLUSH	TCSETSF	/* Flush pending input before changing.  */

  /* line disciplines */
  #define N_TTY		0
  #define N_SLIP		1
  #define N_MOUSE		2
  #define N_PPP		3

  #endif /* __ASM_MIPS_IOCTLS_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/irq.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/irq.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: irq.h
  ===================================================================
  /*
   * include/asm-mips/irq.h
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1994 by Waldorf GMBH
   * written by Ralf Baechle
   *
   */
  #ifndef __ASM_MIPS_IRQ_H
  #define __ASM_MIPS_IRQ_H

  /*
   * Actually this is a lie but we hide the local device's interrupts ...
   */
  #define NR_IRQS 16

  extern void disable_irq(unsigned int);
  extern void enable_irq(unsigned int);

  #endif /* __ASM_MIPS_IRQ_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/jazz.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/jazz.h?rev=1.1&content-type=text/x-cvsweb-markup

  Index: jazz.h
  ===================================================================
  /*
   * Hardware info about Mips JAZZ and similar systems
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file "COPYING" in the main directory of this archive
   * for more details.
   *
   * Copyright (C) 1995 by Andreas Busse and Ralf Baechle
   *
   * This file is a mess. It really needs some reorganisation!
   */

  #ifndef __ASM_MIPS_JAZZ_H 
  #define __ASM_MIPS_JAZZ_H 

  /*
   * The addresses below are virtual address. The mappings are
   * created on startup via wired entries in the tlb. The Mips
   * Magnum R3000 and R4000 machines are similar in many aspects,
   * but many hardware register are accessible at 0xb9000000 in
   * instead of 0xe0000000.
   */

  #define JAZZ_LOCAL_IO_SPACE     0xe0000000

  /*
   * Revision numbers in PICA_ASIC_REVISION
   *
   * 0xf0000000 - Rev1
   * 0xf0000001 - Rev2
   * 0xf0000002 - Rev3
   */
  #define PICA_ASIC_REVISION      0xe0000008

  /*
   * The segments of the seven segment LED are mapped
   * to the control bits as follows:
   *
   *         (7)
   *      ---------
   *      |       |
   *  (2) |       | (6)
   *      |  (1)  |
   *      ---------
   *      |       |
   *  (3) |       | (5)
   *      |  (4)  |
   *      --------- . (0)
   */
  #define PICA_LED                0xe000f000

  /*
   * Some characters for the LED control registers
   * The original Mips machines seem to have a LED display
   * with integrated decoder while the Acer machines can
   * control each of the seven segments and the dot independently.
   * It's only a toy, anyway...
   */
  #define LED_DOT                 0x01
  #define LED_SPACE               0x00
  #define LED_0                   0xfc
  #define LED_1                   0x60
  #define LED_2                   0xda
  #define LED_3                   0xf2
  #define LED_4                   0x66
  #define LED_5                   0xb6
  #define LED_6                   0xbe
  #define LED_7                   0xe0
  #define LED_8                   0xfe
  #define LED_9                   0xf6
  #define LED_A                   0xee
  #define LED_b                   0x3e
  #define LED_C                   0x9c
  #define LED_d                   0x7a
  #define LED_E                   0x9e
  #define LED_F                   0x8e

  #ifndef __LANGUAGE_ASSEMBLY__

  extern __inline__ void pica_set_led(unsigned int bits)
  {
  	volatile unsigned int *led_register = (unsigned int *) PICA_LED;

  	*led_register = bits;
  }

  #endif

  /*
   * i8042 keyboard controller for JAZZ and PICA chipsets.
   * This address is just a guess and seems to differ from
   * other mips machines such as RC3xxx...
   */
  #define JAZZ_KEYBOARD_ADDRESS   0xe0005000
  #define JAZZ_KEYBOARD_DATA      0xe0005000
  #define JAZZ_KEYBOARD_COMMAND   0xe0005001

  #ifndef __LANGUAGE_ASSEMBLY__

  typedef struct {
  	unsigned char data;
  	unsigned char command;
  } jazz_keyboard_hardware;

  typedef struct {
  	unsigned char pad0[3];
  	unsigned char data;
  	unsigned char pad1[3];
  	unsigned char command;
  } mips_keyboard_hardware;

  /*
   * For now. Needs to be changed for RC3xxx support. See below.
   */
  #define keyboard_hardware       jazz_keyboard_hardware

  #endif

  /*
   * i8042 keyboard controller for most other Mips machines.
   */
  #define MIPS_KEYBOARD_ADDRESS   0xb9005000
  #define MIPS_KEYBOARD_DATA      0xb9005003
  #define MIPS_KEYBOARD_COMMAND   0xb9005007

  /*
   * Serial and parallel ports (WD 16C552) on the Mips JAZZ
   */
  #define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
  #define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
  #define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000

  /*
   * Dummy Device Address. Used in jazzdma.c
   */
  #define JAZZ_DUMMY_DEVICE       0xe000d000

  /*
   * JAZZ timer registers and interrupt no.
   * Note that the hardware timer interrupt is actually on
   * cpu level 6, but to keep compatibility with PC stuff
   * it is remapped to vector 0. See arch/mips/kernel/entry.S.
   */
  #define JAZZ_TIMER_INTERVAL     0xe0000228
  #define JAZZ_TIMER_REGISTER     0xe0000230

  /*
   * DRAM configuration register
   */
  #ifndef __LANGUAGE_ASSEMBLY__
  #ifdef __MIPSEL__
  typedef struct {
  	unsigned int bank2 : 3;
  	unsigned int bank1 : 3;
  	unsigned int mem_bus_width : 1;
  	unsigned int reserved2 : 1;
  	unsigned int page_mode : 1;
  	unsigned int reserved1 : 23;
  } dram_configuration;
  #else /* defined (__MIPSEB__) */
  typedef struct {
  	unsigned int reserved1 : 23;
  	unsigned int page_mode : 1;
  	unsigned int reserved2 : 1;
  	unsigned int mem_bus_width : 1;
  	unsigned int bank1 : 3;
  	unsigned int bank2 : 3;
  } dram_configuration;
  #endif
  #endif /* __LANGUAGE_ASSEMBLY__ */

  #define PICA_DRAM_CONFIG        0xe00fffe0

  /*
   * JAZZ interrupt control registers
   */
  #define JAZZ_IO_IRQ_SOURCE      0xe0100000
  #define JAZZ_IO_IRQ_ENABLE      0xe0100002

  /*
   * JAZZ interrupt enable bits
   */
  #define JAZZ_IE_PARALLEL            (1 << 0)
  #define JAZZ_IE_FLOPPY              (1 << 1)
  #define JAZZ_IE_SOUND               (1 << 2)
  #define JAZZ_IE_VIDEO               (1 << 3)
  #define JAZZ_IE_ETHERNET            (1 << 4)
  #define JAZZ_IE_SCSI                (1 << 5)
  #define JAZZ_IE_KEYBOARD            (1 << 6)
  #define JAZZ_IE_MOUSE               (1 << 7)
  #define JAZZ_IE_SERIAL1             (1 << 8)
  #define JAZZ_IE_SERIAL2             (1 << 9)

  /*
   * JAZZ Interrupt Level definitions
   */
  #define JAZZ_TIMER_IRQ          0
  #define JAZZ_KEYBOARD_IRQ       1
  #define JAZZ_ETHERNET_IRQ       2 /* 15 */
  #define JAZZ_SERIAL1_IRQ        3
  #define JAZZ_SERIAL2_IRQ        4
  #define JAZZ_PARALLEL_IRQ       5
  #define JAZZ_FLOPPY_IRQ         6 /* needs to be consistent with floppy driver! */

  /*
   * JAZZ DMA Channels
   * Note: Channels 4...7 are not used with respect to the Acer PICA-61
   * chipset which does not provide these DMA channels.
   */
  #define JAZZ_SCSI_DMA           0              /* SCSI */
  #define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
  #define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
  #define JAZZ_AUDIOR_DMA         3              /* AUDIO R */

  /*
   * JAZZ R4030 MCT_ADR chip (DMA controller)
   * Note: Virtual Addresses !
   */
  #define JAZZ_R4030_CONFIG	0xE0000000	/* R4030 config register */
  #define JAZZ_R4030_REVISION     0xE0000008	/* same as PICA_ASIC_REVISION */
  #define JAZZ_R4030_INV_ADDR	0xE0000010	/* Invalid Address register */

  #define JAZZ_R4030_TRSTBL_BASE  0xE0000018	/* Translation Table Base */
  #define JAZZ_R4030_TRSTBL_LIM   0xE0000020	/* Translation Table Limit */
  #define JAZZ_R4030_TRSTBL_INV   0xE0000028	/* Translation Table Invalidate */

  #define JAZZ_R4030_CACHE_MTNC   0xE0000030	/* Cache Maintenance */
  #define JAZZ_R4030_R_FAIL_ADDR  0xE0000038	/* Remote Failed Address */
  #define JAZZ_R4030_M_FAIL_ADDR  0xE0000040	/* Memory Failed Address */

  #define JAZZ_R4030_CACHE_PTAG   0xE0000048	/* I/O Cache Physical Tag */
  #define JAZZ_R4030_CACHE_LTAG   0xE0000050	/* I/O Cache Logical Tag */
  #define JAZZ_R4030_CACHE_BMASK  0xE0000058	/* I/O Cache Byte Mask */
  #define JAZZ_R4030_CACHE_BWIN   0xE0000060	/* I/O Cache Buffer Window */

  /*
   * Remote Speed Registers. 
   *
   *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
   *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
   *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
   * 12: reserved, 13: free,     14: 7seg LED, 15: ???
   */
  #define JAZZ_R4030_REM_SPEED	0xE0000070	/* 16 Remote Speed Registers */
  						/* 0xE0000070,78,80... 0xE00000E8 */
  #define JAZZ_R4030_IRQ_ENABLE   0xE00000E8	/* Internal Interrupt Enable */

  #define JAZZ_R4030_IRQ_SOURCE   0xE0000200	/* Interrupt Source Reg */
  #define JAZZ_R4030_I386_ERROR   0xE0000208	/* i386/EISA Bus Error */

  /*
   * Access the R4030 DMA and I/O Controller
   */
  #ifndef __LANGUAGE_ASSEMBLY__

  extern inline unsigned short r4030_read_reg16(unsigned addr) {
  	unsigned short ret = *((volatile unsigned short *)addr);
  	__asm__ __volatile__(
  		".set\tnoreorder\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		".set\treorder");
  	return ret;
  }

  extern inline unsigned int r4030_read_reg32(unsigned addr) {
  	unsigned int ret = *((volatile unsigned int *)addr);
  	__asm__ __volatile__(
  		".set\tnoreorder\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		".set\treorder");
  	return ret;
  }

  extern inline void r4030_write_reg16(unsigned addr, unsigned val) {
  	*((volatile unsigned short *)addr) = val;
  	__asm__ __volatile__(
  		".set\tnoreorder\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		".set\treorder");
  }

  extern inline unsigned int r4030_write_reg32(unsigned addr, unsigned val) {
  	*((volatile unsigned int *)addr) = val;
  	__asm__ __volatile__(
  		".set\tnoreorder\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		"nop\n\t"
  		".set\treorder");
  }

  #endif /* !LANGUAGE_ASSEMBLY__ */

  #define JAZZ_FDC_BASE 0xe0003000

  #define JAZZ_RTC_BASE 0xe0004000

  #endif /* __ASM_MIPS_JAZZ_H */

  1.1                  or1k/rc203soc/sw/uClinux/include/asm-mips/jazzdma.h

  http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-mips/jazzdma.h?rev=1.1&content-type=text/x-cv