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From: cvs at opencores.org<cvs@o...>
Date: Tue Dec 20 12:35:39 CET 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/12 20:12:35

Added: or1k/rc203soc/sw/uClinux/include/asm-i386 a.out.h atomic.h
bitops.h bugs.h byteorder.h checksum.h delay.h
dma.h elf.h errno.h fcntl.h floppy.h i82489.h io.h
ioctl.h ioctls.h irq.h locks.h math_emu.h mman.h
mmu_context.h mtrr.h page.h param.h pgtable.h
posix_types.h processor.h ptrace.h resource.h
segment.h semaphore.h setup.h shmparam.h
sigcontext.h signal.h smp.h smp_lock.h socket.h
sockios.h stat.h statfs.h string-486.h string.h
system.h termbits.h termios.h types.h unaligned.h
unistd.h user.h vm86.h
Log:
First Import of RC20x uClinux


Revision Changes Path
1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/a.out.h

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/a.out.h?rev=1.1&content-type=text/x-cvsweb-markup

Index: a.out.h
===================================================================
#ifndef __I386_A_OUT_H__
#define __I386_A_OUT_H__

struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};

#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)

#ifdef __KERNEL__

#define STACK_TOP TASK_SIZE

#endif

#endif /* __A_OUT_GNU_H__ */



1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/atomic.h

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/atomic.h?rev=1.1&content-type=text/x-cvsweb-markup

Index: atomic.h
===================================================================
#ifndef __ARCH_I386_ATOMIC__
#define __ARCH_I386_ATOMIC__

/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/

#ifdef __SMP__
#define LOCK "lock ; "
#else
#define LOCK ""
#endif

/*
* Make sure gcc doesn't try to be clever and move things around
* on us. We need to use _exactly_ the address the user gave us,
* not some alias that contains the same information.
*/
#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x)

typedef int atomic_t;

static __inline__ void atomic_add(atomic_t i, atomic_t *v)
{
__asm__ __volatile__(
LOCK "addl %1,%0"
:"=m" (__atomic_fool_gcc(v))
:"ir" (i), "m" (__atomic_fool_gcc(v)));
}

static __inline__ void atomic_sub(atomic_t i, atomic_t *v)
{
__asm__ __volatile__(
LOCK "subl %1,%0"
:"=m" (__atomic_fool_gcc(v))
:"ir" (i), "m" (__atomic_fool_gcc(v)));
}

static __inline__ void atomic_inc(atomic_t *v)
{
__asm__ __volatile__(
LOCK "incl %0"
:"=m" (__atomic_fool_gcc(v)) :"m" (__atomic_fool_gcc(v))); } static __inline__ void atomic_dec(atomic_t *v) { __asm__ __volatile__( LOCK "decl %0" :"=m" (__atomic_fool_gcc(v)) :"m" (__atomic_fool_gcc(v))); } static __inline__ int atomic_dec_and_test(atomic_t *v) { unsigned char c; __asm__ __volatile__( LOCK "decl %0; sete %1" :"=m" (__atomic_fool_gcc(v)), "=qm" (c) :"m" (__atomic_fool_gcc(v))); return c != 0; } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/bitops.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/bitops.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bitops.h =================================================================== #ifndef _I386_BITOPS_H #define _I386_BITOPS_H /* * Copyright 1992, Linus Torvalds. */ /* * These have to be done with inline assembly: that way the bit-setting * is guaranteed to be atomic. All bit operations return 0 if the bit * was cleared before the operation and != 0 if it was not. * * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). */ #ifdef __SMP__ #define LOCK_PREFIX "lock ; " #define SMPVOL volatile #else #define LOCK_PREFIX "" #define SMPVOL #endif /* * Some hacks to defeat gcc over-optimizations.. */ struct __dummy { unsigned long a[100]; }; #define ADDR (*(struct __dummy *) addr) #define CONST_ADDR (*(const struct __dummy *) addr) extern __inline__ int set_bit(int nr, SMPVOL void * addr) { int oldbit; __asm__ __volatile__(LOCK_PREFIX "btsl %2,%1\n\tsbbl %0,%0" :"=r" (oldbit),"=m" (ADDR) :"ir" (nr)); return oldbit; } extern __inline__ int clear_bit(int nr, SMPVOL void * addr) { int oldbit; __asm__ __volatile__(LOCK_PREFIX "btrl %2,%1\n\tsbbl %0,%0" :"=r" (oldbit),"=m" (ADDR) :"ir" (nr)); return oldbit; } extern __inline__ int change_bit(int nr, SMPVOL void * addr) { int oldbit; __asm__ __volatile__(LOCK_PREFIX "btcl %2,%1\n\tsbbl %0,%0" :"=r" (oldbit),"=m" (ADDR) :"ir" (nr)); return oldbit; } /* * This routine doesn't need to be atomic. */ extern __inline__ int test_bit(int nr, const SMPVOL void * addr) { return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; } /* * Find-bit routines.. */ extern __inline__ int find_first_zero_bit(void * addr, unsigned size) { int res; if (!size) return 0; __asm__("cld\n\t" "movl $-1,%%eax\n\t" "xorl %%edx,%%edx\n\t" "repe; scasl\n\t" "je 1f\n\t" "xorl -4(%%edi),%%eax\n\t" "subl $4,%%edi\n\t" "bsfl %%eax,%%edx\n" "1:\tsubl %%ebx,%%edi\n\t" "shll $3,%%edi\n\t" "addl %%edi,%%edx" :"=d" (res) :"c" ((size + 31) >> 5), "D" (addr), "b" (addr) :"ax", "cx", "di"); return res; } extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) { unsigned long * p = ((unsigned long *) addr) + (offset >> 5); int set = 0, bit = offset & 31, res; if (bit) { /* * Look for zero in first byte */ __asm__("bsfl %1,%0\n\t" "jne 1f\n\t" "movl $32, %0\n" "1:" : "=r" (set) : "r" (~(*p >> bit))); if (set < (32 - bit)) return set + offset; set = 32 - bit; p++; } /* * No zero yet, search remaining full bytes for a zero */ res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr)); return (offset + set + res); } /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ extern __inline__ unsigned long ffz(unsigned long word) { __asm__("bsfl %1,%0" :"=r" (word) :"r" (~word)); return word; } #endif /* _I386_BITOPS_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/bugs.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/bugs.h?rev=1.1&content-type=text/x-cvsweb-markup Index: bugs.h =================================================================== /* * include/asm-i386/bugs.h * * Copyright (C) 1994 Linus Torvalds */ /* * This is included by init/main.c to check for architecture-dependent bugs. * * Needs: * void check_bugs(void); */ #include <linux/config.h> #define CONFIG_BUGi386 static void no_halt(char *s, int *ints) { hlt_works_ok = 0; } static void no_387(char *s, int *ints) { hard_math = 0; __asm__("movl %%cr0,%%eax\n\t" "orl $0xE,%%eax\n\t" "movl %%eax,%%cr0\n\t" : : : "ax"); } static char fpu_error = 0; static void copro_timeout(void) { fpu_error = 1; timer_table[COPRO_TIMER].expires = jiffies+100; timer_active |= 1<<COPRO_TIMER; printk("387 failed: trying to reset\n"); send_sig(SIGFPE, last_task_used_math, 1); outb_p(0,0xf1); outb_p(0,0xf0); } static void check_fpu(void) { static double x = 4195835.0; static double y = 3145727.0; unsigned short control_word; if (!hard_math) { #ifndef CONFIG_MATH_EMULATION printk("No coprocessor found and no math emulation present.\n"); printk("Giving up.\n"); for (;;) ; #endif return; } /* * check if exception 16 works correctly.. This is truly evil * code: it disables the high 8 interrupts to make sure that * the irq13 doesn't happen. But as this will lead to a lockup * if no exception16 arrives, it depends on the fact that the * high 8 interrupts will be re-enabled by the next timer tick. * So the irq13 will happen eventually, but the exception 16 * should get there first.. */ printk("Checking 386/387 coupling... "); timer_table[COPRO_TIMER].expires = jiffies+50; timer_table[COPRO_TIMER].fn = copro_timeout; timer_active |= 1<<COPRO_TIMER; __asm__("clts ; fninit ; fnstcw %0 ; fwait":"=m" (*&control_word)); control_word &= 0xffc0; __asm__("fldcw %0 ; fwait": :"m" (*&control_word)); outb_p(inb_p(0x21) | (1 << 2), 0x21); __asm__("fldz ; fld1 ; fdiv %st,%st(1) ; fwait"); timer_active &= ~(1<<COPRO_TIMER); if (fpu_error) return; if (!ignore_irq13) { printk("Ok, fpu using old IRQ13 error reporting\n"); return; } __asm__("fninit\n\t" "fldl %1\n\t" "fdivl %2\n\t" "fmull %2\n\t" "fldl %1\n\t" "fsubp %%st,%%st(1)\n\t" "fistpl %0\n\t" "fwait\n\t" "fninit" : "=m" (*&fdiv_bug) : "m" (*&x), "m" (*&y)); if (!fdiv_bug) { printk("Ok, fpu using exception 16 error reporting.\n"); return; } printk("Hmm, FDIV bug i%c86 system\n", '0'+x86); } static void check_hlt(void) { printk("Checking 'hlt' instruction... "); if (!hlt_works_ok) { printk("disabled\n"); return; } __asm__ __volatile__("hlt ; hlt ; hlt ; hlt"); printk("Ok.\n"); } static void check_tlb(void) { #ifndef CONFIG_M386 /* * The 386 chips don't support TLB finegrained invalidation. * They will fault when they hit a invlpg instruction. */ if (x86 == 3) { printk("CPU is a 386 and this kernel was compiled for 486 or better.\n"); printk("Giving up.\n"); for (;;) ; } #endif } /* * All current models of Pentium and Pentium with MMX technology CPUs * have the F0 0F bug, which lets nonpriviledged users lock up the system: */ extern int pentium_f00f_bug; extern void trap_init_f00f_bug(void); /* * Access to machine-specific registers (available on 586 and better only) * Note: the rd* operations modify the parameters directly (without using * pointer indirection), this allows gcc to optimize better * Code from Richard Gooch's 2.2 MTRR drivers. */ #define rdmsr(msr,val1,val2) \ __asm__ __volatile__("rdmsr" \ : "=a" (val1), "=d" (val2) \ : "c" (msr)) #define wrmsr(msr,val1,val2) \ __asm__ __volatile__("wrmsr" \ : /* no outputs */ \ : "c" (msr), "a" (val1), "d" (val2)) static void check_pentium_f00f(void) { /* * Pentium and Pentium MMX */ pentium_f00f_bug = 0; if (x86==5 && !memcmp(x86_vendor_id, "GenuineIntel", 12)) { printk(KERN_INFO "Intel Pentium with F0 0F bug - workaround enabled.\n"); pentium_f00f_bug = 1; trap_init_f00f_bug(); } } static void check_privacy(void) { /* * Pentium III or higher - processors with mtrrs/cpuid */ if(memcmp(x86_vendor_id, "GenuineIntel", 12)) return; if(x86_capability & (1<<18)) { /* * Thanks to Phil Karn for this bit. */ unsigned long lo,hi; rdmsr(0x119,lo,hi); lo |= 0x200000; wrmsr(0x119,lo,hi); printk(KERN_INFO "Pentium-III serial number disabled.\n"); } } /* * B step AMD K6 before B 9730xxxx have hardware bugs that can cause * misexecution of code under Linux. Owners of such processors should * contact AMD for precise details and a (free) CPU exchange. * * See http://www.chorus.com/~poulot/k6bug.html * http://www.amd.com/K6/k6docs/revgd.html * * The following test is erm... interesting. AMD neglected to up * the chip stepping when fixing the bug but they also tweaked some * performance at the same time... */ extern void vide(void); __asm__(".align 4\nvide: ret"); static void check_k6_bug(void) { if ((strcmp(x86_vendor_id, "AuthenticAMD") == 0) && (x86_model == 6) && (x86_mask == 1)) { int n; void (*f_vide)(void); unsigned long d, d2; printk(KERN_INFO "AMD K6 stepping B detected - "); #define K6_BUG_LOOP 1000000 /* * It looks like AMD fixed the 2.6.2 bug and improved indirect * calls at the same time. */ n = K6_BUG_LOOP; f_vide = vide; __asm__ ("rdtsc" : "=a" (d)); while (n--) f_vide(); __asm__ ("rdtsc" : "=a" (d2)); d = d2-d; if (d > 20*K6_BUG_LOOP) { printk("system stability may be impaired when more than 32 MB are used.\n"); } else printk("probably OK (after B9730xxxx).\n"); } } /* Cyrix stuff from this point on */ /* Cyrix 5/2 test (return 0x200 if it's a Cyrix) */ static inline int test_cyrix_52div(void) { int test; __asm__ __volatile__("xor %%eax,%%eax\n\t" "sahf\n\t" "movb $5,%%al\n\t" "movb $2,%%bl\n\t" "div %%bl\n\t" "lahf\n\t" "andl $0xff00,%%eax": "=eax" (test) : : "bx"); return test; } /* test for CCR3 bit 7 r/w */ static char test_cyrix_cr3rw(void) { char temp, test; temp = getCx86(CX86_CCR3); /* get current CCR3 value */ setCx86(CX86_CCR3, temp ^ 0x80); /* toggle test bit and write */ getCx86(0xc0); /* dummy to change bus */ test = temp - getCx86(CX86_CCR3); /* != 0 if ccr3 r/w */ setCx86(CX86_CCR3, temp); /* return CCR3 to original value */ return test; } /* redo the cpuid test in head.S, so that those 6x86(L) now get detected properly (0 == no cpuid) */ static inline int test_cpuid(void) { int test; __asm__("pushfl\n\t" "popl %%eax\n\t" "movl %%eax,%%ecx\n\t" "xorl $0x200000,%%eax\n\t" "pushl %%eax\n\t" "popfl\n\t" "pushfl\n\t" "popl %%eax\n\t" "xorl %%ecx,%%eax\n\t" "pushl %%ecx\n\t" "popfl" : "=eax" (test) : : "cx"); return test; } /* All Cyrix 6x86 and 6x86L need the SLOP bit reset so that the udelay loop * calibration works well. * This routine must be called with MAPEN enabled, otherwise we don't * have access to CCR5. */ static void check_6x86_slop(void) { if (x86_model == 2) /* if 6x86 or 6x86L */ setCx86(CX86_CCR5, getCx86(CX86_CCR5) & 0xfd); /* reset SLOP */ } /* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected * by the fact that they preserve the flags across the division of 5/2. * PII and PPro exhibit this behavior too, but they have cpuid available. */ static void check_cyrix_various(void) { if ((x86 == 4) && (test_cyrix_52div()==0x200)) { /* if it's a Cyrix */ unsigned long flags; /* default to an "old" Cx486 */ strcpy(x86_vendor_id, "CyrixInstead"); x86_model = -1; x86_mask = 0; /* Disable interrupts */ save_flags(flags); cli(); /* First check for very old CX486 models */ /* that did not have DIR0/DIR1. */ if (test_cyrix_cr3rw()) { /* if has DIR0/DIR1 */ char ccr3; char dir0; x86_model = 0; /* Enable MAPEN */ ccr3 = getCx86(CX86_CCR3); setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); dir0 = getCx86(CX86_DIR0); if ((dir0 & 0xf0) == 0x30) /* Use DIR0 to determine if this is a 6x86 class processor */ { /* try enabling cpuid */ setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80); } if (test_cpuid()) { int eax, dummy; /* get processor info */ cpuid(1, &eax, &dummy, &dummy, &x86_capability); have_cpuid = 1; x86_model = (eax >> 4) & 0xf; x86 = (eax >> 8) & 0xf; check_6x86_slop(); } /* disable MAPEN */ setCx86(CX86_CCR3, ccr3); } /* endif has DIR0/DIR1 */ sti(); restore_flags(flags); /* restore interrupt state */ } /* endif it's a Cyrix */ } /* Check various processor bugs */ static void check_bugs(void) { check_cyrix_various(); check_k6_bug(); check_tlb(); check_fpu(); check_hlt(); check_pentium_f00f(); check_privacy(); system_utsname.machine[1] = '0' + x86; } 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/byteorder.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/byteorder.h?rev=1.1&content-type=text/x-cvsweb-markup Index: byteorder.h =================================================================== #ifndef _I386_BYTEORDER_H #define _I386_BYTEORDER_H #undef ntohl #undef ntohs #undef htonl #undef htons #ifndef __LITTLE_ENDIAN #define __LITTLE_ENDIAN 1234 #endif #ifndef __LITTLE_ENDIAN_BITFIELD #define __LITTLE_ENDIAN_BITFIELD #endif /* For avoiding bswap on i386 */ #ifdef __KERNEL__ #include <linux/config.h> #endif extern unsigned long int ntohl(unsigned long int); extern unsigned short int ntohs(unsigned short int); extern unsigned long int htonl(unsigned long int); extern unsigned short int htons(unsigned short int); extern __inline__ unsigned long int __ntohl(unsigned long int); extern __inline__ unsigned short int __ntohs(unsigned short int); extern __inline__ unsigned long int __constant_ntohl(unsigned long int); extern __inline__ unsigned short int __constant_ntohs(unsigned short int); extern __inline__ unsigned long int __ntohl(unsigned long int x) { #if defined(__KERNEL__) && !defined(CONFIG_M386) __asm__("bswap %0" : "=r" (x) : "0" (x)); #else __asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */ "rorl $16,%0\n\t" /* swap words */ "xchgb %b0,%h0" /* swap higher bytes */ :"=q" (x) : "0" (x)); #endif return x; } #define __constant_ntohl(x) \ ((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \ (((unsigned long int)(x) & 0x0000ff00U) << 8) | \ (((unsigned long int)(x) & 0x00ff0000U) >> 8) | \ (((unsigned long int)(x) & 0xff000000U) >> 24))) extern __inline__ unsigned short int __ntohs(unsigned short int x) { __asm__("xchgb %b0,%h0" /* swap bytes */ : "=q" (x) : "0" (x)); return x; } #define __constant_ntohs(x) \ ((unsigned short int)((((unsigned short int)(x) & 0x00ff) << 8) | \ (((unsigned short int)(x) & 0xff00) >> 8))) \ #define __htonl(x) __ntohl(x) #define __htons(x) __ntohs(x) #define __constant_htonl(x) __constant_ntohl(x) #define __constant_htons(x) __constant_ntohs(x) #ifdef __OPTIMIZE__ # define ntohl(x) \ (__builtin_constant_p((long)(x)) ? \ __constant_ntohl((x)) : \ __ntohl((x))) # define ntohs(x) \ (__builtin_constant_p((short)(x)) ? \ __constant_ntohs((x)) : \ __ntohs((x))) # define htonl(x) \ (__builtin_constant_p((long)(x)) ? \ __constant_htonl((x)) : \ __htonl((x))) # define htons(x) \ (__builtin_constant_p((short)(x)) ? \ __constant_htons((x)) : \ __htons((x))) #endif #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/checksum.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/checksum.h?rev=1.1&content-type=text/x-cvsweb-markup Index: checksum.h =================================================================== #ifndef _I386_CHECKSUM_H #define _I386_CHECKSUM_H /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) * * returns a 32-bit number suitable for feeding into itself * or csum_tcpudp_magic * * this function must be called with even lengths, except * for the last fragment, which may be odd * * it's best to have buff aligned on a 32-bit boundary */ unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum); /* * the same as csum_partial, but copies from src while it * checksums * * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ unsigned int csum_partial_copy( const char *src, char *dst, int len, int sum); /* * the same as csum_partial_copy, but copies from user space. * * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ unsigned int csum_partial_copy_fromuser(const char *src, char *dst, int len, int sum); /* * This is a version of ip_compute_csum() optimized for IP headers, * which always checksum on 4 octet boundaries. * * By Jorge Cwik <jorge@l...>, adapted for linux by * Arnt Gulbrandsen. */ static inline unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl) { unsigned int sum; __asm__ __volatile__(" movl (%1), %0 subl $4, %2 jbe 2f addl 4(%1), %0 adcl 8(%1), %0 adcl 12(%1), %0 1: adcl 16(%1), %0 lea 4(%1), %1 decl %2 jne 1b adcl $0, %0 movl %0, %2 shrl $16, %0 addw %w2, %w0 adcl $0, %0 notl %0 2: " /* Since the input registers which are loaded with iph and ipl are modified, we must also specify them as outputs, or gcc will assume they contain their original values. */ : "=r" (sum), "=r" (iph), "=r" (ihl) : "1" (iph), "2" (ihl)); return(sum); } /* * Fold a partial checksum */ static inline unsigned int csum_fold(unsigned int sum) { __asm__(" addl %1, %0 adcl $0xffff, %0 " : "=r" (sum) : "r" (sum << 16), "0" (sum & 0xffff0000) ); return (~sum) >> 16; } /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ static inline unsigned short int csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len, unsigned short proto, unsigned int sum) { __asm__(" addl %1, %0 adcl %2, %0 adcl %3, %0 adcl $0, %0 " : "=r" (sum) : "g" (daddr), "g"(saddr), "g"((ntohs(len)<<16)+proto*256), "0"(sum)); return csum_fold(sum); } /* * this routine is used for miscellaneous IP-like checksums, mainly * in icmp.c */ static inline unsigned short ip_compute_csum(unsigned char * buff, int len) { return csum_fold (csum_partial(buff, len, 0)); } #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/delay.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/delay.h?rev=1.1&content-type=text/x-cvsweb-markup Index: delay.h =================================================================== #ifndef _I386_DELAY_H #define _I386_DELAY_H /* * Copyright (C) 1993 Linus Torvalds * * Delay routines, using a pre-computed "loops_per_second" value. */ #include <linux/linkage.h> #ifdef __SMP__ #include <asm/smp.h> #endif extern void __do_delay(void); /* Special register call calling convention */ extern __inline__ void __delay(int loops) { __asm__ __volatile__( "call " SYMBOL_NAME_STR(__do_delay) :/* no outputs */ :"a" (loops) :"ax"); } /* * division by multiplication: you don't have to worry about * loss of precision. * * Use only for very small delays ( < 1 msec). Should probably use a * lookup table, really, as the multiplications take much too long with * short delays. This is a "reasonable" implementation, though (and the * first constant multiplications gets optimized away if the delay is * a constant) */ extern __inline__ void udelay(unsigned long usecs) { usecs *= 0x000010c6; /* 2**32 / 1000000 */ __asm__("mull %0" :"=d" (usecs) #ifdef __SMP__ :"a" (usecs),"0" (cpu_data[smp_processor_id()].udelay_val) #else :"a" (usecs),"0" (loops_per_sec) #endif :"ax"); __delay(usecs); } extern __inline__ unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c) { __asm__("mull %1 ; divl %2" :"=a" (a) :"d" (b), "r" (c), "0" (a) :"dx"); return a; } #endif /* defined(_I386_DELAY_H) */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/dma.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/dma.h?rev=1.1&content-type=text/x-cvsweb-markup Index: dma.h =================================================================== /* $Id: dma.h,v 1.1 2005/12/20 11:35:33 jcastillo Exp $ * linux/include/asm/dma.h: Defines for using and allocating dma channels. * Written by Hennus Bergman, 1992. * High DMA channel support & info by Hannu Savolainen * and John Boyd, Nov. 1992. */ #ifndef _ASM_DMA_H #define _ASM_DMA_H #include <asm/io.h> /* need byte IO */ #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER #define dma_outb outb_p #else #define dma_outb outb #endif #define dma_inb inb /* * NOTES about DMA transfers: * * controller 1: channels 0-3, byte operations, ports 00-1F * controller 2: channels 4-7, word operations, ports C0-DF * * - ALL registers are 8 bits only, regardless of transfer size * - channel 4 is not used - cascades 1 into 2. * - channels 0-3 are byte - addresses/counts are for physical bytes * - channels 5-7 are word - addresses/counts are for physical words * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries * - transfer count loaded to registers is 1 less than actual count * - controller 2 offsets are all even (2x offsets for controller 1) * - page registers for 5-7 don't use data bit 0, represent 128K pages * - page registers for 0-3 use bit 0, represent 64K pages * * DMA transfers are limited to the lower 16MB of _physical_ memory. * Note that addresses loaded into registers must be _physical_ addresses, * not logical addresses (which may differ if paging is active). * * Address mapping for channels 0-3: * * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) * | ... | | ... | | ... | * | ... | | ... | | ... | * | ... | | ... | | ... | * P7 ... P0 A7 ... A0 A7 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Address mapping for channels 5-7: * * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) * | ... | \ \ ... \ \ \ ... \ \ * | ... | \ \ ... \ \ \ ... \ (not used) * | ... | \ \ ... \ \ \ ... \ * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at * the hardware level, so odd-byte transfers aren't possible). * * Transfer count (_not # bytes_) is limited to 64K, represented as actual * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, * and up to 128K bytes may be transferred on channels 5-7 in one operation. * */ #define MAX_DMA_CHANNELS 8 /* The maximum address that we can perform a DMA transfer to on this platform */ #define MAX_DMA_ADDRESS 0x1000000 /* 8237 DMA controllers */ #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ #define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ #define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ #define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ #define DMA_ADDR_0 0x00 /* DMA address registers */ #define DMA_ADDR_1 0x02 #define DMA_ADDR_2 0x04 #define DMA_ADDR_3 0x06 #define DMA_ADDR_4 0xC0 #define DMA_ADDR_5 0xC4 #define DMA_ADDR_6 0xC8 #define DMA_ADDR_7 0xCC #define DMA_CNT_0 0x01 /* DMA count registers */ #define DMA_CNT_1 0x03 #define DMA_CNT_2 0x05 #define DMA_CNT_3 0x07 #define DMA_CNT_4 0xC2 #define DMA_CNT_5 0xC6 #define DMA_CNT_6 0xCA #define DMA_CNT_7 0xCE #define DMA_PAGE_0 0x87 /* DMA page registers */ #define DMA_PAGE_1 0x83 #define DMA_PAGE_2 0x81 #define DMA_PAGE_3 0x82 #define DMA_PAGE_5 0x8B #define DMA_PAGE_6 0x89 #define DMA_PAGE_7 0x8A #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ /* enable/disable a specific DMA channel */ static __inline__ void enable_dma(unsigned int dmanr) { if (dmanr<=3) dma_outb(dmanr, DMA1_MASK_REG); else dma_outb(dmanr & 3, DMA2_MASK_REG); } static __inline__ void disable_dma(unsigned int dmanr) { if (dmanr<=3) dma_outb(dmanr | 4, DMA1_MASK_REG); else dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); } /* Clear the 'DMA Pointer Flip Flop'. * Write 0 for LSB/MSB, 1 for MSB/LSB access. * Use this once to initialize the FF to a known state. * After that, keep track of it. :-) * --- In order to do that, the DMA routines below should --- * --- only be used while interrupts are disabled! --- */ static __inline__ void clear_dma_ff(unsigned int dmanr) { if (dmanr<=3) dma_outb(0, DMA1_CLEAR_FF_REG); else dma_outb(0, DMA2_CLEAR_FF_REG); } /* set mode (above) for a specific DMA channel */ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { if (dmanr<=3) dma_outb(mode | dmanr, DMA1_MODE_REG); else dma_outb(mode | (dmanr&3), DMA2_MODE_REG); } /* Set only the page register bits of the transfer address. * This is used for successive transfers when we know the contents of * the lower 16 bits of the DMA current address register, but a 64k boundary * may have been crossed. */ static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) { switch(dmanr) { case 0: dma_outb(pagenr, DMA_PAGE_0); break; case 1: dma_outb(pagenr, DMA_PAGE_1); break; case 2: dma_outb(pagenr, DMA_PAGE_2); break; case 3: dma_outb(pagenr, DMA_PAGE_3); break; case 5: dma_outb(pagenr & 0xfe, DMA_PAGE_5); break; case 6: dma_outb(pagenr & 0xfe, DMA_PAGE_6); break; case 7: dma_outb(pagenr & 0xfe, DMA_PAGE_7); break; } } /* Set transfer address & page bits for specific DMA channel. * Assumes dma flipflop is clear. */ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) { set_dma_page(dmanr, a>>16); if (dmanr <= 3) { dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); } else { dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); } } /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for * a specific DMA channel. * You must ensure the parameters are valid. * NOTE: from a manual: "the number of transfers is one more * than the initial word count"! This is taken into account. * Assumes dma flip-flop is clear. * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. */ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) { count--; if (dmanr <= 3) { dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); } else { dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); } } /* Get DMA residue count. After a DMA transfer, this * should return zero. Reading this while a DMA transfer is * still in progress will return unpredictable results. * If called before the channel has been used, it may return 1. * Otherwise, it returns the number of _bytes_ left to transfer. * * Assumes DMA flip-flop is clear. */ static __inline__ int get_dma_residue(unsigned int dmanr) { unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; /* using short to get 16-bit wrap around */ unsigned short count; count = 1 + dma_inb(io_port); count += dma_inb(io_port) << 8; return (dmanr<=3)? count : (count<<1); } /* These are in kernel/dma.c: */ extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ #endif /* _ASM_DMA_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/elf.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/elf.h?rev=1.1&content-type=text/x-cvsweb-markup Index: elf.h =================================================================== #ifndef __ASMi386_ELF_H #define __ASMi386_ELF_H /* * ELF register definitions.. */ #include <asm/ptrace.h> typedef unsigned long elf_greg_t; #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef struct user_i387_struct elf_fpregset_t; /* * This is used to ensure we don't load something for the wrong architecture. */ #define elf_check_arch(x) ( ((x) == EM_386) || ((x) == EM_486) ) /* * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS32 #define ELF_DATA ELFDATA2LSB; #define ELF_ARCH EM_386 /* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program starts %edx contains a pointer to a function which might be registered using `atexit'. This provides a mean for the dynamic linker to call DT_FINI functions for shared libraries that have been loaded before the code runs. A value of 0 tells we have no such handler. */ #define ELF_PLAT_INIT(_r) _r->edx = 0 #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/errno.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/errno.h?rev=1.1&content-type=text/x-cvsweb-markup Index: errno.h =================================================================== #ifndef _I386_ERRNO_H #define _I386_ERRNO_H #define EPERM 1 /* Operation not permitted */ #define ENOENT 2 /* No such file or directory */ #define ESRCH 3 /* No such process */ #define EINTR 4 /* Interrupted system call */ #define EIO 5 /* I/O error */ #define ENXIO 6 /* No such device or address */ #define E2BIG 7 /* Arg list too long */ #define ENOEXEC 8 /* Exec format error */ #define EBADF 9 /* Bad file number */ #define ECHILD 10 /* No child processes */ #define EAGAIN 11 /* Try again */ #define ENOMEM 12 /* Out of memory */ #define EACCES 13 /* Permission denied */ #define EFAULT 14 /* Bad address */ #define ENOTBLK 15 /* Block device required */ #define EBUSY 16 /* Device or resource busy */ #define EEXIST 17 /* File exists */ #define EXDEV 18 /* Cross-device link */ #define ENODEV 19 /* No such device */ #define ENOTDIR 20 /* Not a directory */ #define EISDIR 21 /* Is a directory */ #define EINVAL 22 /* Invalid argument */ #define ENFILE 23 /* File table overflow */ #define EMFILE 24 /* Too many open files */ #define ENOTTY 25 /* Not a typewriter */ #define ETXTBSY 26 /* Text file busy */ #define EFBIG 27 /* File too large */ #define ENOSPC 28 /* No space left on device */ #define ESPIPE 29 /* Illegal seek */ #define EROFS 30 /* Read-only file system */ #define EMLINK 31 /* Too many links */ #define EPIPE 32 /* Broken pipe */ #define EDOM 33 /* Math argument out of domain of func */ #define ERANGE 34 /* Math result not representable */ #define EDEADLK 35 /* Resource deadlock would occur */ #define ENAMETOOLONG 36 /* File name too long */ #define ENOLCK 37 /* No record locks available */ #define ENOSYS 38 /* Function not implemented */ #define ENOTEMPTY 39 /* Directory not empty */ #define ELOOP 40 /* Too many symbolic links encountered */ #define EWOULDBLOCK EAGAIN /* Operation would block */ #define ENOMSG 42 /* No message of desired type */ #define EIDRM 43 /* Identifier removed */ #define ECHRNG 44 /* Channel number out of range */ #define EL2NSYNC 45 /* Level 2 not synchronized */ #define EL3HLT 46 /* Level 3 halted */ #define EL3RST 47 /* Level 3 reset */ #define ELNRNG 48 /* Link number out of range */ #define EUNATCH 49 /* Protocol driver not attached */ #define ENOCSI 50 /* No CSI structure available */ #define EL2HLT 51 /* Level 2 halted */ #define EBADE 52 /* Invalid exchange */ #define EBADR 53 /* Invalid request descriptor */ #define EXFULL 54 /* Exchange full */ #define ENOANO 55 /* No anode */ #define EBADRQC 56 /* Invalid request code */ #define EBADSLT 57 /* Invalid slot */ #define EDEADLOCK EDEADLK #define EBFONT 59 /* Bad font file format */ #define ENOSTR 60 /* Device not a stream */ #define ENODATA 61 /* No data available */ #define ETIME 62 /* Timer expired */ #define ENOSR 63 /* Out of streams resources */ #define ENONET 64 /* Machine is not on the network */ #define ENOPKG 65 /* Package not installed */ #define EREMOTE 66 /* Object is remote */ #define ENOLINK 67 /* Link has been severed */ #define EADV 68 /* Advertise error */ #define ESRMNT 69 /* Srmount error */ #define ECOMM 70 /* Communication error on send */ #define EPROTO 71 /* Protocol error */ #define EMULTIHOP 72 /* Multihop attempted */ #define EDOTDOT 73 /* RFS specific error */ #define EBADMSG 74 /* Not a data message */ #define EOVERFLOW 75 /* Value too large for defined data type */ #define ENOTUNIQ 76 /* Name not unique on network */ #define EBADFD 77 /* File descriptor in bad state */ #define EREMCHG 78 /* Remote address changed */ #define ELIBACC 79 /* Can not access a needed shared library */ #define ELIBBAD 80 /* Accessing a corrupted shared library */ #define ELIBSCN 81 /* .lib section in a.out corrupted */ #define ELIBMAX 82 /* Attempting to link in too many shared libraries */ #define ELIBEXEC 83 /* Cannot exec a shared library directly */ #define EILSEQ 84 /* Illegal byte sequence */ #define ERESTART 85 /* Interrupted system call should be restarted */ #define ESTRPIPE 86 /* Streams pipe error */ #define EUSERS 87 /* Too many users */ #define ENOTSOCK 88 /* Socket operation on non-socket */ #define EDESTADDRREQ 89 /* Destination address required */ #define EMSGSIZE 90 /* Message too long */ #define EPROTOTYPE 91 /* Protocol wrong type for socket */ #define ENOPROTOOPT 92 /* Protocol not available */ #define EPROTONOSUPPORT 93 /* Protocol not supported */ #define ESOCKTNOSUPPORT 94 /* Socket type not supported */ #define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ #define EPFNOSUPPORT 96 /* Protocol family not supported */ #define EAFNOSUPPORT 97 /* Address family not supported by protocol */ #define EADDRINUSE 98 /* Address already in use */ #define EADDRNOTAVAIL 99 /* Cannot assign requested address */ #define ENETDOWN 100 /* Network is down */ #define ENETUNREACH 101 /* Network is unreachable */ #define ENETRESET 102 /* Network dropped connection because of reset */ #define ECONNABORTED 103 /* Software caused connection abort */ #define ECONNRESET 104 /* Connection reset by peer */ #define ENOBUFS 105 /* No buffer space available */ #define EISCONN 106 /* Transport endpoint is already connected */ #define ENOTCONN 107 /* Transport endpoint is not connected */ #define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ #define ETOOMANYREFS 109 /* Too many references: cannot splice */ #define ETIMEDOUT 110 /* Connection timed out */ #define ECONNREFUSED 111 /* Connection refused */ #define EHOSTDOWN 112 /* Host is down */ #define EHOSTUNREACH 113 /* No route to host */ #define EALREADY 114 /* Operation already in progress */ #define EINPROGRESS 115 /* Operation now in progress */ #define ESTALE 116 /* Stale NFS file handle */ #define EUCLEAN 117 /* Structure needs cleaning */ #define ENOTNAM 118 /* Not a XENIX named type file */ #define ENAVAIL 119 /* No XENIX semaphores available */ #define EISNAM 120 /* Is a named type file */ #define EREMOTEIO 121 /* Remote I/O error */ #define EDQUOT 122 /* Quota exceeded */ #define ENOMEDIUM 123 /* No medium found */ #define EMEDIUMTYPE 124 /* Wrong medium type */ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/fcntl.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/fcntl.h?rev=1.1&content-type=text/x-cvsweb-markup Index: fcntl.h =================================================================== #ifndef _I386_FCNTL_H #define _I386_FCNTL_H /* open/fcntl - O_SYNC is only implemented on blocks devices and on files located on an ext2 file system */ #define O_ACCMODE 0003 #define O_RDONLY 00 #define O_WRONLY 01 #define O_RDWR 02 #define O_CREAT 0100 /* not fcntl */ #define O_EXCL 0200 /* not fcntl */ #define O_NOCTTY 0400 /* not fcntl */ #define O_TRUNC 01000 /* not fcntl */ #define O_APPEND 02000 #define O_NONBLOCK 04000 #define O_NDELAY O_NONBLOCK #define O_SYNC 010000 #define FASYNC 020000 /* fcntl, for BSD compatibility */ #define F_DUPFD 0 /* dup */ #define F_GETFD 1 /* get f_flags */ #define F_SETFD 2 /* set f_flags */ #define F_GETFL 3 /* more flags (cloexec) */ #define F_SETFL 4 #define F_GETLK 5 #define F_SETLK 6 #define F_SETLKW 7 #define F_SETOWN 8 /* for sockets. */ #define F_GETOWN 9 /* for sockets. */ /* for F_[GET|SET]FL */ #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ /* for posix fcntl() and lockf() */ #define F_RDLCK 0 #define F_WRLCK 1 #define F_UNLCK 2 /* for old implementation of bsd flock () */ #define F_EXLCK 4 /* or 3 */ #define F_SHLCK 8 /* or 4 */ /* operations for bsd flock(), also used by the kernel implementation */ #define LOCK_SH 1 /* shared lock */ #define LOCK_EX 2 /* exclusive lock */ #define LOCK_NB 4 /* or'd with one of the above to prevent blocking */ #define LOCK_UN 8 /* remove lock */ struct flock { short l_type; short l_whence; off_t l_start; off_t l_len; pid_t l_pid; }; #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/floppy.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/floppy.h?rev=1.1&content-type=text/x-cvsweb-markup Index: floppy.h =================================================================== /* * Architecture specific parts of the Floppy driver * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995 */ #ifndef __ASM_I386_FLOPPY_H #define __ASM_I386_FLOPPY_H #define SW fd_routine[use_virtual_dma&1] #define fd_inb(port) inb_p(port) #define fd_outb(port,value) outb_p(port,value) #define fd_enable_dma() SW._enable_dma(FLOPPY_DMA) #define fd_disable_dma() SW._disable_dma(FLOPPY_DMA) #define fd_request_dma() SW._request_dma(FLOPPY_DMA,"floppy") #define fd_free_dma() SW._free_dma(FLOPPY_DMA) #define fd_clear_dma_ff() SW._clear_dma_ff(FLOPPY_DMA) #define fd_set_dma_mode(mode) SW._set_dma_mode(FLOPPY_DMA,mode) #define fd_set_dma_addr(addr) SW._set_dma_addr(FLOPPY_DMA,addr) #define fd_set_dma_count(count) SW._set_dma_count(FLOPPY_DMA,count) #define fd_enable_irq() enable_irq(FLOPPY_IRQ) #define fd_disable_irq() disable_irq(FLOPPY_IRQ) #define fd_cacheflush(addr,size) /* nothing */ #define fd_request_irq() SW._request_irq(FLOPPY_IRQ, floppy_interrupt, \ SA_INTERRUPT|SA_SAMPLE_RANDOM, \ "floppy", NULL) #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL) #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA) #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size) #define fd_dma_mem_free(addr,size) SW._dma_mem_free(addr,size) static int virtual_dma_count=0; static int virtual_dma_residue=0; static unsigned long virtual_dma_addr=0; static int virtual_dma_mode=0; static int doing_pdma=0; static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs) { register unsigned char st; #undef TRACE_FLPY_INT #undef NO_FLOPPY_ASSEMBLER #ifdef TRACE_FLPY_INT static int calls=0; static int bytes=0; static int dma_wait=0; #endif if(!doing_pdma) { floppy_interrupt(irq, dev_id, regs); return; } #ifdef TRACE_FLPY_INT if(!calls) bytes = virtual_dma_count; #endif #ifndef NO_FLOPPY_ASSEMBLER __asm__ ( "testl %1,%1 je 3f 1: inb %w4,%b0 andb $160,%b0 cmpb $160,%b0 jne 2f incw %w4 testl %3,%3 jne 4f inb %w4,%b0 movb %0,(%2) jmp 5f 4: movb (%2),%0 outb %b0,%w4 5: decw %w4 outb %0,$0x80 decl %1 incl %2 testl %1,%1 jne 1b 3: inb %w4,%b0 2: " : "=a" ((char) st), "=c" ((long) virtual_dma_count), "=S" ((long) virtual_dma_addr) : "b" ((long) virtual_dma_mode), "d" ((short) virtual_dma_port+4), "1" ((long) virtual_dma_count), "2" ((long) virtual_dma_addr)); #else { register int lcount; register char *lptr; st = 1; for(lcount=virtual_dma_count, lptr=(char *)virtual_dma_addr; lcount; lcount--, lptr++) { st=inb(virtual_dma_port+4) & 0xa0 ; if(st != 0xa0) break; if(virtual_dma_mode) outb_p(*lptr, virtual_dma_port+5); else *lptr = inb_p(virtual_dma_port+5); st = inb(virtual_dma_port+4); } virtual_dma_count = lcount; virtual_dma_addr = (int) lptr; } #endif #ifdef TRACE_FLPY_INT calls++; #endif if(st == 0x20) return; if(!(st & 0x20)) { virtual_dma_residue += virtual_dma_count; virtual_dma_count=0; #ifdef TRACE_FLPY_INT printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", virtual_dma_count, virtual_dma_residue, calls, bytes, dma_wait); calls = 0; dma_wait=0; #endif doing_pdma = 0; floppy_interrupt(irq, dev_id, regs); return; } #ifdef TRACE_FLPY_INT if(!virtual_dma_count) dma_wait++; #endif } static void vdma_enable_dma(unsigned int dummy) { doing_pdma = 1; } static void vdma_disable_dma(unsigned int dummy) { doing_pdma = 0; virtual_dma_residue += virtual_dma_count; virtual_dma_count=0; } static int vdma_request_dma(unsigned int dmanr, const char * device_id) { return 0; } static void vdma_nop(unsigned int dummy) { } static void vdma_set_dma_mode(unsigned int dummy,char mode) { virtual_dma_mode = (mode == DMA_MODE_WRITE); } static void vdma_set_dma_addr(unsigned int dummy,unsigned int addr) { virtual_dma_addr = addr; } static void vdma_set_dma_count(unsigned int dummy,unsigned int count) { virtual_dma_count = count; virtual_dma_residue = 0; } static int vdma_get_dma_residue(unsigned int dummy) { return virtual_dma_count + virtual_dma_residue; } static int vdma_request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *device, void *dev_id) { return request_irq(irq, floppy_hardint,SA_INTERRUPT,device, dev_id); } static unsigned long dma_mem_alloc(unsigned long size) { return __get_dma_pages(GFP_KERNEL,__get_order(size)); } static void dma_mem_free(unsigned long addr, unsigned long size) { free_pages(addr, __get_order(size)); } static unsigned long vdma_mem_alloc(unsigned long size) { return (unsigned long) vmalloc(size); } static void vdma_mem_free(unsigned long addr, unsigned long size) { return vfree((void *)addr); } struct fd_routine_l { void (*_enable_dma)(unsigned int dummy); void (*_disable_dma)(unsigned int dummy); int (*_request_dma)(unsigned int dmanr, const char * device_id); void (*_free_dma)(unsigned int dmanr); void (*_clear_dma_ff)(unsigned int dummy); void (*_set_dma_mode)(unsigned int dummy, char mode); void (*_set_dma_addr)(unsigned int dummy, unsigned int addr); void (*_set_dma_count)(unsigned int dummy, unsigned int count); int (*_get_dma_residue)(unsigned int dummy); int (*_request_irq)(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *device, void *dev_id); unsigned long (*_dma_mem_alloc) (unsigned long size); void (*_dma_mem_free)(unsigned long addr, unsigned long size); } fd_routine[] = { { enable_dma, disable_dma, request_dma, free_dma, clear_dma_ff, set_dma_mode, set_dma_addr, set_dma_count, get_dma_residue, request_irq, dma_mem_alloc, dma_mem_free }, { vdma_enable_dma, vdma_disable_dma, vdma_request_dma, vdma_nop, vdma_nop, vdma_set_dma_mode, vdma_set_dma_addr, vdma_set_dma_count, vdma_get_dma_residue, vdma_request_irq, vdma_mem_alloc, vdma_mem_free } }; __inline__ void virtual_dma_init(void) { /* Nothing to do on an i386 */ } static int FDC1 = 0x3f0; static int FDC2 = -1; #define FLOPPY0_TYPE ((CMOS_READ(0x10) >> 4) & 15) #define FLOPPY1_TYPE (CMOS_READ(0x10) & 15) #define N_FDC 2 #define N_DRIVE 8 /* * The DMA channel used by the floppy controller cannot access data at * addresses >= 16MB * * Went back to the 1MB limit, as some people had problems with the floppy * driver otherwise. It doesn't matter much for performance anyway, as most * floppy accesses go through the track buffer. */ #define CROSS_64KB(a,s) (((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) && ! (use_virtual_dma & 1)) #endif /* __ASM_I386_FLOPPY_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/i82489.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/i82489.h?rev=1.1&content-type=text/x-cvsweb-markup Index: i82489.h =================================================================== #ifndef __ASM_I82489_H #define __ASM_I82489_H /* * Offsets for programming the 82489 and Pentium integrated APIC * * Alan Cox <Alan.Cox@l...>, 1995. */ #define APIC_ID 0x20 #define GET_APIC_ID(x) (((x)>>24)&0x0F) #define APIC_VERSION 0x30 #define APIC_TASKPRI 0x80 #define APIC_TPRI_MASK 0xFF #define APIC_ARBPRI 0x90 #define APIC_PROCPRI 0xA0 #define APIC_EOI 0xB0 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */ #define APIC_RRR 0xC0 #define APIC_LDR 0xD0 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF) #define APIC_DFR 0xE0 #define GET_APIC_DFR(x) (((x)>>28)&0x0F) #define SET_APIC_DFR(x) ((x)<<28) #define APIC_SPIV 0xF0 #define APIC_ISR 0x100 #define APIC_TMR 0x180 #define APIC_IRR 0x200 #define APIC_ESR 0x280 #define APIC_ESR_SEND_CS 0x00001 #define APIC_ESR_RECV_CS 0x00002 #define APIC_ESR_SEND_ACC 0x00004 #define APIC_ESR_RECV_ACC 0x00008 #define APIC_ESR_SENDILL 0x00020 #define APIC_ESR_RECVILL 0x00040 #define APIC_ESR_ILLREGA 0x00080 #define APIC_ICR 0x300 #define APIC_DEST_FIELD 0x00000 #define APIC_DEST_SELF 0x40000 #define APIC_DEST_ALLINC 0x80000 #define APIC_DEST_ALLBUT 0xC0000 #define APIC_DEST_RR_MASK 0x30000 #define APIC_DEST_RR_INVALID 0x00000 #define APIC_DEST_RR_INPROG 0x10000 #define APIC_DEST_RR_VALID 0x20000 #define APIC_DEST_LEVELTRIG 0x08000 #define APIC_DEST_ASSERT 0x04000 #define APIC_DEST_BUSY 0x01000 #define APIC_DEST_LOGICAL 0x00800 #define APIC_DEST_DM_FIXED 0x00000 #define APIC_DEST_DM_LOWEST 0x00100 #define APIC_DEST_DM_SMI 0x00200 #define APIC_DEST_DM_REMRD 0x00300 #define APIC_DEST_DM_NMI 0x00400 #define APIC_DEST_DM_INIT 0x00500 #define APIC_DEST_DM_STARTUP 0x00600 #define APIC_DEST_VECTOR_MASK 0x000FF #define APIC_ICR2 0x310 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) #define SET_APIC_DEST_FIELD(x) ((x)<<24) #define APIC_LVTT 0x320 #define APIC_LVT0 0x350 #define APIC_LVT_TIMER_PERIODIC (1<<17) #define APIC_LVT_MASKED (1<<16) #define APIC_LVT_LEVEL_TRIGGER (1<<15) #define APIC_LVT_REMOTE_IRR (1<<14) #define APIC_INPUT_POLARITY (1<<13) #define APIC_SEND_PENDING (1<<12) #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) #define APIC_MODE_FIXED 0x0 #define APIC_MODE_NMI 0x4 #define APIC_MODE_EXINT 0x7 #define APIC_LVT1 0x360 #define APIC_LVERR 0x370 #define APIC_TMICT 0x380 #define APIC_TMCCT 0x390 #define APIC_TDCR 0x3E0 #define APIC_TDR_DIV_1 0xB #define APIC_TDR_DIV_2 0x0 #define APIC_TDR_DIV_4 0x1 #define APIC_TDR_DIV_8 0x2 #define APIC_TDR_DIV_16 0x3 #define APIC_TDR_DIV_32 0x8 #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/io.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/io.h?rev=1.1&content-type=text/x-cvsweb-markup Index: io.h =================================================================== #ifndef _ASM_IO_H #define _ASM_IO_H /* * This file contains the definitions for the x86 IO instructions * inb/inw/inl/outb/outw/outl and the "string versions" of the same * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" * versions of the single-IO instructions (inb_p/inw_p/..). * * This file is not meant to be obfuscating: it's just complicated * to (a) handle it all in a way that makes gcc able to optimize it * as well as possible and (b) trying to avoid writing the same thing * over and over again with slight variations and possibly making a * mistake somewhere. */ /* * Thanks to James van Artsdalen for a better timing-fix than * the two short jumps: using outb's to a nonexistent port seems * to guarantee better timings even on fast machines. * * On the other hand, I'd like to be sure of a non-existent port: * I feel a bit unsafe about using 0x80 (should be safe, though) * * Linus */ #ifdef SLOW_IO_BY_JUMPING #define __SLOW_DOWN_IO __asm__ __volatile__("jmp 1f\n1:\tjmp 1f\n1:") #else #define __SLOW_DOWN_IO __asm__ __volatile__("outb %al,$0x80") #endif #ifdef REALLY_SLOW_IO #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } #else #define SLOW_DOWN_IO __SLOW_DOWN_IO #endif /* * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/i386 mapping (but if we ever * make the kernel segment mapped at 0, we need to do translation * on the i386 as well) */ extern inline unsigned long virt_to_phys(volatile void * address) { return (unsigned long) address; } extern inline void * phys_to_virt(unsigned long address) { return (void *) address; } /* * IO bus memory addresses are also 1:1 with the physical address */ #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt /* * readX/writeX() are used to access memory mapped devices. On some * architectures the memory mapped IO stuff needs to be accessed * differently. On the x86 architecture, we just read/write the * memory location directly. */ #define readb(addr) (*(volatile unsigned char *) (addr)) #define readw(addr) (*(volatile unsigned short *) (addr)) #define readl(addr) (*(volatile unsigned int *) (addr)) #define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) #define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) #define memset_io(a,b,c) memset((void *)(a),(b),(c)) #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) /* * Again, i386 does not require mem IO specific function. */ #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d)) /* * Talk about misusing macros.. */ #define __OUT1(s,x) \ extern inline void __out##s(unsigned x value, unsigned short port) { #define __OUT2(s,s1,s2) \ __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1" #define __OUT(s,s1,x) \ __OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "d" (port)); } \ __OUT1(s##c,x) __OUT2(s,s1,"") : : "a" (value), "id" (port)); } \ __OUT1(s##_p,x) __OUT2(s,s1,"w") : : "a" (value), "d" (port)); SLOW_DOWN_IO; } \ __OUT1(s##c_p,x) __OUT2(s,s1,"") : : "a" (value), "id" (port)); SLOW_DOWN_IO; } #define __IN1(s) \ extern inline RETURN_TYPE __in##s(unsigned short port) { RETURN_TYPE _v; #define __IN2(s,s1,s2) \ __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0" #define __IN(s,s1,i...) \ __IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "d" (port) ,##i ); return _v; } \ __IN1(s##c) __IN2(s,s1,"") : "=a" (_v) : "id" (port) ,##i ); return _v; } \ __IN1(s##_p) __IN2(s,s1,"w") : "=a" (_v) : "d" (port) ,##i ); SLOW_DOWN_IO; return _v; } \ __IN1(s##c_p) __IN2(s,s1,"") : "=a" (_v) : "id" (port) ,##i ); SLOW_DOWN_IO; return _v; } #define __INS(s) \ extern inline void ins##s(unsigned short port, void * addr, unsigned long count) \ { __asm__ __volatile__ ("cld ; rep ; ins" #s \ : "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } #define __OUTS(s) \ extern inline void outs##s(unsigned short port, const void * addr, unsigned long count) \ { __asm__ __volatile__ ("cld ; rep ; outs" #s \ : "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } #define RETURN_TYPE unsigned char /* __IN(b,"b","0" (0)) */ __IN(b,"") #undef RETURN_TYPE #define RETURN_TYPE unsigned short /* __IN(w,"w","0" (0)) */ __IN(w,"") #undef RETURN_TYPE #define RETURN_TYPE unsigned int __IN(l,"") #undef RETURN_TYPE __OUT(b,"b",char) __OUT(w,"w",short) __OUT(l,,int) __INS(b) __INS(w) __INS(l) __OUTS(b) __OUTS(w) __OUTS(l) /* * Note that due to the way __builtin_constant_p() works, you * - can't use it inside a inline function (it will never be true) * - you don't have to worry about side effects within the __builtin.. */ #define outb(val,port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __outbc((val),(port)) : \ __outb((val),(port))) #define inb(port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __inbc(port) : \ __inb(port)) #define outb_p(val,port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __outbc_p((val),(port)) : \ __outb_p((val),(port))) #define inb_p(port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __inbc_p(port) : \ __inb_p(port)) #define outw(val,port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __outwc((val),(port)) : \ __outw((val),(port))) #define inw(port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __inwc(port) : \ __inw(port)) #define outw_p(val,port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __outwc_p((val),(port)) : \ __outw_p((val),(port))) #define inw_p(port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __inwc_p(port) : \ __inw_p(port)) #define outl(val,port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __outlc((val),(port)) : \ __outl((val),(port))) #define inl(port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __inlc(port) : \ __inl(port)) #define outl_p(val,port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __outlc_p((val),(port)) : \ __outl_p((val),(port))) #define inl_p(port) \ ((__builtin_constant_p((port)) && (port) < 256) ? \ __inlc_p(port) : \ __inl_p(port)) #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/ioctl.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/ioctl.h?rev=1.1&content-type=text/x-cvsweb-markup Index: ioctl.h =================================================================== /* $Id: ioctl.h,v 1.1 2005/12/20 11:35:33 jcastillo Exp $ * * linux/ioctl.h for Linux by H.H. Bergman. */ #ifndef _ASMI386_IOCTL_H #define _ASMI386_IOCTL_H /* ioctl command encoding: 32 bits total, command in lower 16 bits, * size of the parameter structure in the lower 14 bits of the * upper 16 bits. * Encoding the size of the parameter structure in the ioctl request * is useful for catching programs compiled with old versions * and to avoid overwriting user space outside the user buffer area. * The highest 2 bits are reserved for indicating the ``access mode''. * NOTE: This limits the max parameter size to 16kB -1 ! */ /* * The following is for compatibility across the various Linux * platforms. The i386 ioctl numbering scheme doesn't really enforce * a type field. De facto, however, the top 8 bits of the lower 16 * bits are indeed used as a type field, so we might just as well make * this explicit here. Please be sure to use the decoding macros * below from now on. */ #define _IOC_NRBITS 8 #define _IOC_TYPEBITS 8 #define _IOC_SIZEBITS 14 #define _IOC_DIRBITS 2 #define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) #define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) #define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) #define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) #define _IOC_NRSHIFT 0 #define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) #define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) #define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) /* * Direction bits. */ #define _IOC_NONE 0U #define _IOC_WRITE 1U #define _IOC_READ 2U #define _IOC(dir,type,nr,size) \ (((dir) << _IOC_DIRSHIFT) | \ ((type) << _IOC_TYPESHIFT) | \ ((nr) << _IOC_NRSHIFT) | \ ((size) << _IOC_SIZESHIFT)) /* used to create numbers */ #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) /* used to decode ioctl numbers.. */ #define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) #define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) #define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) /* ...and for the drivers/sound files... */ #define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) #define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) #define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) #define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) #define IOCSIZE_SHIFT (_IOC_SIZESHIFT) #endif /* _ASMI386_IOCTL_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/ioctls.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/ioctls.h?rev=1.1&content-type=text/x-cvsweb-markup Index: ioctls.h =================================================================== #ifndef __ARCH_I386_IOCTLS_H__ #define __ARCH_I386_IOCTLS_H__ #include <asm/ioctl.h> /* 0x54 is just a magic number to make these relatively unique ('T') */ #define TCGETS 0x5401 #define TCSETS 0x5402 #define TCSETSW 0x5403 #define TCSETSF 0x5404 #define TCGETA 0x5405 #define TCSETA 0x5406 #define TCSETAW 0x5407 #define TCSETAF 0x5408 #define TCSBRK 0x5409 #define TCXONC 0x540A #define TCFLSH 0x540B #define TIOCEXCL 0x540C #define TIOCNXCL 0x540D #define TIOCSCTTY 0x540E #define TIOCGPGRP 0x540F #define TIOCSPGRP 0x5410 #define TIOCOUTQ 0x5411 #define TIOCSTI 0x5412 #define TIOCGWINSZ 0x5413 #define TIOCSWINSZ 0x5414 #define TIOCMGET 0x5415 #define TIOCMBIS 0x5416 #define TIOCMBIC 0x5417 #define TIOCMSET 0x5418 #define TIOCGSOFTCAR 0x5419 #define TIOCSSOFTCAR 0x541A #define FIONREAD 0x541B #define TIOCINQ FIONREAD #define TIOCLINUX 0x541C #define TIOCCONS 0x541D #define TIOCGSERIAL 0x541E #define TIOCSSERIAL 0x541F #define TIOCPKT 0x5420 #define FIONBIO 0x5421 #define TIOCNOTTY 0x5422 #define TIOCSETD 0x5423 #define TIOCGETD 0x5424 #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ #define TIOCTTYGSTRUCT 0x5426 /* For debugging only */ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ #define FIOCLEX 0x5451 #define FIOASYNC 0x5452 #define TIOCSERCONFIG 0x5453 #define TIOCSERGWILD 0x5454 #define TIOCSERSWILD 0x5455 #define TIOCGLCKTRMIOS 0x5456 #define TIOCSLCKTRMIOS 0x5457 #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ #define TIOCSERGETLSR 0x5459 /* Get line status register */ #define TIOCSERGETMULTI 0x545A /* Get multiport config */ #define TIOCSERSETMULTI 0x545B /* Set multiport config */ #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ /* Used for packet mode */ #define TIOCPKT_DATA 0 #define TIOCPKT_FLUSHREAD 1 #define TIOCPKT_FLUSHWRITE 2 #define TIOCPKT_STOP 4 #define TIOCPKT_START 8 #define TIOCPKT_NOSTOP 16 #define TIOCPKT_DOSTOP 32 #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/irq.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/irq.h?rev=1.1&content-type=text/x-cvsweb-markup Index: irq.h =================================================================== #ifndef _ASM_IRQ_H #define _ASM_IRQ_H /* * linux/include/asm/irq.h * * (C) 1992, 1993 Linus Torvalds * * IRQ/IPI changes taken from work by Thomas Radke <tomsoft@i...> */ #include <linux/linkage.h> #include <asm/segment.h> #define NR_IRQS 16 #define TIMER_IRQ 0 extern void disable_irq(unsigned int); extern void enable_irq(unsigned int); #define __STR(x) #x #define STR(x) __STR(x) #define SAVE_ALL \ "cld\n\t" \ "push %gs\n\t" \ "push %fs\n\t" \ "push %es\n\t" \ "push %ds\n\t" \ "pushl %eax\n\t" \ "pushl %ebp\n\t" \ "pushl %edi\n\t" \ "pushl %esi\n\t" \ "pushl %edx\n\t" \ "pushl %ecx\n\t" \ "pushl %ebx\n\t" \ "movl $" STR(KERNEL_DS) ",%edx\n\t" \ "mov %dx,%ds\n\t" \ "mov %dx,%es\n\t" \ "movl $" STR(USER_DS) ",%edx\n\t" \ "mov %dx,%fs\n\t" \ "movl $0,%edx\n\t" \ "movl %edx,%db7\n\t" /* * SAVE_MOST/RESTORE_MOST is used for the faster version of IRQ handlers, * installed by using the SA_INTERRUPT flag. These kinds of IRQ's don't * call the routines that do signal handling etc on return, and can have * more relaxed register-saving etc. They are also atomic, and are thus * suited for small, fast interrupts like the serial lines or the harddisk * drivers, which don't actually need signal handling etc. * * Also note that we actually save only those registers that are used in * C subroutines (%eax, %edx and %ecx), so if you do something weird, * you're on your own. The only segments that are saved (not counting the * automatic stack and code segment handling) are %ds and %es, and they * point to kernel space. No messing around with %fs here. */ #define SAVE_MOST \ "cld\n\t" \ "push %es\n\t" \ "push %ds\n\t" \ "pushl %eax\n\t" \ "pushl %edx\n\t" \ "pushl %ecx\n\t" \ "movl $" STR(KERNEL_DS) ",%edx\n\t" \ "mov %dx,%ds\n\t" \ "mov %dx,%es\n\t" #define RESTORE_MOST \ "popl %ecx\n\t" \ "popl %edx\n\t" \ "popl %eax\n\t" \ "pop %ds\n\t" \ "pop %es\n\t" \ "iret" /* * The "inb" instructions are not needed, but seem to change the timings * a bit - without them it seems that the harddisk driver won't work on * all hardware. Arghh. */ #define ACK_FIRST(mask,nr) \ "inb $0x21,%al\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\torb $" #mask ","SYMBOL_NAME_STR(cache_21)"\n\t" \ "movb "SYMBOL_NAME_STR(cache_21)",%al\n\t" \ "outb %al,$0x21\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\tmovb $0x20,%al\n\t" \ "outb %al,$0x20\n\t" #define ACK_SECOND(mask,nr) \ "inb $0xA1,%al\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\torb $" #mask ","SYMBOL_NAME_STR(cache_A1)"\n\t" \ "movb "SYMBOL_NAME_STR(cache_A1)",%al\n\t" \ "outb %al,$0xA1\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\tmovb $0x20,%al\n\t" \ "outb %al,$0xA0\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\toutb %al,$0x20\n\t" /* do not modify the ISR nor the cache_A1 variable */ #define MSGACK_SECOND(mask,nr) \ "inb $0xA1,%al\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\tmovb $0x20,%al\n\t" \ "outb %al,$0xA0\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\toutb %al,$0x20\n\t" #define UNBLK_FIRST(mask) \ "inb $0x21,%al\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\tandb $~(" #mask "),"SYMBOL_NAME_STR(cache_21)"\n\t" \ "movb "SYMBOL_NAME_STR(cache_21)",%al\n\t" \ "outb %al,$0x21\n\t" #define UNBLK_SECOND(mask) \ "inb $0xA1,%al\n\t" \ "jmp 1f\n" \ "1:\tjmp 1f\n" \ "1:\tandb $~(" #mask "),"SYMBOL_NAME_STR(cache_A1)"\n\t" \ "movb "SYMBOL_NAME_STR(cache_A1)",%al\n\t" \ "outb %al,$0xA1\n\t" #define IRQ_NAME2(nr) nr##_interrupt(void) #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) #define FAST_IRQ_NAME(nr) IRQ_NAME2(fast_IRQ##nr) #define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) #ifdef __SMP__ #ifndef __SMP_PROF__ #define SMP_PROF_INT_SPINS #define SMP_PROF_IPI_CNT #else #define SMP_PROF_INT_SPINS "incl "SYMBOL_NAME_STR(smp_spins)"(,%eax,4)\n\t" #define SMP_PROF_IPI_CNT "incl "SYMBOL_NAME_STR(ipi_count)"\n\t" #endif #define GET_PROCESSOR_ID \ "movl "SYMBOL_NAME_STR(apic_reg)", %edx\n\t" \ "movl 32(%edx), %eax\n\t" \ "shrl $24,%eax\n\t" \ "andl $0x0F,%eax\n" #define ENTER_KERNEL \ "pushl %eax\n\t" \ "pushl %ebx\n\t" \ "pushl %ecx\n\t" \ "pushl %edx\n\t" \ "pushfl\n\t" \ "cli\n\t" \ "movl $6000, %ebx\n\t" \ "movl "SYMBOL_NAME_STR(smp_loops_per_tick)", %ecx\n\t" \ GET_PROCESSOR_ID \ "btsl $" STR(SMP_FROM_INT) ","SYMBOL_NAME_STR(smp_proc_in_lock)"(,%eax,4)\n\t" \ "1: " \ "lock\n\t" \ "btsl $0, "SYMBOL_NAME_STR(kernel_flag)"\n\t" \ "jnc 3f\n\t" \ "cmpb "SYMBOL_NAME_STR(active_kernel_processor)", %al\n\t" \ "je 4f\n\t" \ "cmpb "SYMBOL_NAME_STR(boot_cpu_id)", %al\n\t" \ "jne 2f\n\t" \ "movb $1, "SYMBOL_NAME_STR(smp_blocked_interrupt_pending)"\n\t" \ "2: " \ SMP_PROF_INT_SPINS \ "btl %eax, "SYMBOL_NAME_STR(smp_invalidate_needed)"\n\t" \ "jnc 5f\n\t" \ "lock\n\t" \ "btrl %eax, "SYMBOL_NAME_STR(smp_invalidate_needed)"\n\t" \ "jnc 5f\n\t" \ "movl %cr3,%edx\n\t" \ "movl %edx,%cr3\n" \ "5: btl $0, "SYMBOL_NAME_STR(kernel_flag)"\n\t" \ "jnc 1b\n\t" \ "cmpb "SYMBOL_NAME_STR(active_kernel_processor)", %al\n\t" \ "je 4f\n\t" \ "decl %ecx\n\t" \ "jne 2b\n\t" \ "decl %ebx\n\t" \ "jne 6f\n\t" \ "call "SYMBOL_NAME_STR(irq_deadlock_detected)"\n\t" \ "6: movl "SYMBOL_NAME_STR(smp_loops_per_tick)", %ecx\n\t" \ "cmpb "SYMBOL_NAME_STR(boot_cpu_id)", %al\n\t" \ "jne 2b\n\t" \ "incl "SYMBOL_NAME_STR(jiffies)"\n\t" \ "jmp 2b\n\t" \ "3: " \ "movb %al, "SYMBOL_NAME_STR(active_kernel_processor)"\n\t" \ "4: " \ "incl "SYMBOL_NAME_STR(kernel_counter)"\n\t" \ "cmpb "SYMBOL_NAME_STR(boot_cpu_id)", %al\n\t" \ "jne 7f\n\t" \ "movb $0, "SYMBOL_NAME_STR(smp_blocked_interrupt_pending)"\n\t" \ "7: " \ "popfl\n\t" \ "popl %edx\n\t" \ "popl %ecx\n\t" \ "popl %ebx\n\t" \ "popl %eax\n\t" #define LEAVE_KERNEL \ GET_PROCESSOR_ID \ "btrl $" STR(SMP_FROM_INT) ","SYMBOL_NAME_STR(smp_proc_in_lock)"(,%eax,4)\n\t" \ "pushfl\n\t" \ "cli\n\t" \ "decl "SYMBOL_NAME_STR(kernel_counter)"\n\t" \ "jnz 1f\n\t" \ "movb "SYMBOL_NAME_STR(saved_active_kernel_processor)",%al\n\t" \ "movb %al,"SYMBOL_NAME_STR(active_kernel_processor)"\n\t" \ "cmpb $" STR (NO_PROC_ID) ",%al\n\t" \ "jne 1f\n\t" \ "lock\n\t" \ "btrl $0, "SYMBOL_NAME_STR(kernel_flag)"\n\t" \ "1: " \ "popfl\n\t" /* * the syscall count inc is a gross hack because ret_from_syscall is used by both irq and * syscall return paths (urghh). */ #define BUILD_IRQ(chip,nr,mask) \ asmlinkage void IRQ_NAME(nr); \ asmlinkage void FAST_IRQ_NAME(nr); \ asmlinkage void BAD_IRQ_NAME(nr); \ __asm__( \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \ "pushl $-"#nr"-2\n\t" \ SAVE_ALL \ ENTER_KERNEL \ ACK_##chip(mask,(nr&7)) \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t"\ "sti\n\t" \ "movl %esp,%ebx\n\t" \ "pushl %ebx\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_IRQ)"\n\t" \ "addl $8,%esp\n\t" \ "cli\n\t" \ UNBLK_##chip(mask) \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "incl "SYMBOL_NAME_STR(syscall_count)"\n\t" \ "jmp ret_from_sys_call\n" \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(fast_IRQ) #nr "_interrupt:\n\t" \ SAVE_MOST \ ENTER_KERNEL \ ACK_##chip(mask,(nr&7)) \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_fast_IRQ)"\n\t" \ "addl $4,%esp\n\t" \ "cli\n\t" \ UNBLK_##chip(mask) \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ LEAVE_KERNEL \ RESTORE_MOST \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(bad_IRQ) #nr "_interrupt:\n\t" \ SAVE_MOST \ ENTER_KERNEL \ ACK_##chip(mask,(nr&7)) \ LEAVE_KERNEL \ RESTORE_MOST); #define BUILD_TIMER_IRQ(chip,nr,mask) \ asmlinkage void IRQ_NAME(nr); \ asmlinkage void FAST_IRQ_NAME(nr); \ asmlinkage void BAD_IRQ_NAME(nr); \ __asm__( \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(fast_IRQ) #nr "_interrupt:\n\t" \ SYMBOL_NAME_STR(bad_IRQ) #nr "_interrupt:\n\t" \ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \ "pushl $-"#nr"-2\n\t" \ SAVE_ALL \ ENTER_KERNEL \ ACK_##chip(mask,(nr&7)) \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t"\ "movl %esp,%ebx\n\t" \ "pushl %ebx\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_IRQ)"\n\t" \ "addl $8,%esp\n\t" \ "cli\n\t" \ UNBLK_##chip(mask) \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "incl "SYMBOL_NAME_STR(syscall_count)"\n\t" \ "jmp ret_from_sys_call\n"); /* * Message pass must be a fast IRQ.. */ #define BUILD_MSGIRQ(chip,nr,mask) \ asmlinkage void IRQ_NAME(nr); \ asmlinkage void FAST_IRQ_NAME(nr); \ asmlinkage void BAD_IRQ_NAME(nr); \ __asm__( \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \ SYMBOL_NAME_STR(fast_IRQ) #nr "_interrupt:\n\t" \ SAVE_MOST \ MSGACK_##chip(mask,(nr&7)) \ SMP_PROF_IPI_CNT \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_fast_IRQ)"\n\t" \ "addl $4,%esp\n\t" \ "cli\n\t" \ RESTORE_MOST \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(bad_IRQ) #nr "_interrupt:\n\t" \ SAVE_MOST \ ACK_##chip(mask,(nr&7)) \ RESTORE_MOST); #define BUILD_RESCHEDIRQ(nr) \ asmlinkage void IRQ_NAME(nr); \ __asm__( \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \ "pushl $-"#nr"-2\n\t" \ SAVE_ALL \ ENTER_KERNEL \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t"\ "sti\n\t" \ "movl %esp,%ebx\n\t" \ "pushl %ebx\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(smp_reschedule_irq)"\n\t" \ "addl $8,%esp\n\t" \ "cli\n\t" \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "incl "SYMBOL_NAME_STR(syscall_count)"\n\t" \ "jmp ret_from_sys_call\n"); #else #define BUILD_IRQ(chip,nr,mask) \ asmlinkage void IRQ_NAME(nr); \ asmlinkage void FAST_IRQ_NAME(nr); \ asmlinkage void BAD_IRQ_NAME(nr); \ __asm__( \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \ "pushl $-"#nr"-2\n\t" \ SAVE_ALL \ ACK_##chip(mask,(nr&7)) \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t"\ "sti\n\t" \ "movl %esp,%ebx\n\t" \ "pushl %ebx\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_IRQ)"\n\t" \ "addl $8,%esp\n\t" \ "cli\n\t" \ UNBLK_##chip(mask) \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "jmp ret_from_sys_call\n" \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(fast_IRQ) #nr "_interrupt:\n\t" \ SAVE_MOST \ ACK_##chip(mask,(nr&7)) \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_fast_IRQ)"\n\t" \ "addl $4,%esp\n\t" \ "cli\n\t" \ UNBLK_##chip(mask) \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ RESTORE_MOST \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(bad_IRQ) #nr "_interrupt:\n\t" \ SAVE_MOST \ ACK_##chip(mask,(nr&7)) \ RESTORE_MOST); #define BUILD_TIMER_IRQ(chip,nr,mask) \ asmlinkage void IRQ_NAME(nr); \ asmlinkage void FAST_IRQ_NAME(nr); \ asmlinkage void BAD_IRQ_NAME(nr); \ __asm__( \ "\n"__ALIGN_STR"\n" \ SYMBOL_NAME_STR(fast_IRQ) #nr "_interrupt:\n\t" \ SYMBOL_NAME_STR(bad_IRQ) #nr "_interrupt:\n\t" \ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \ "pushl $-"#nr"-2\n\t" \ SAVE_ALL \ ACK_##chip(mask,(nr&7)) \ "incl "SYMBOL_NAME_STR(intr_count)"\n\t"\ "movl %esp,%ebx\n\t" \ "pushl %ebx\n\t" \ "pushl $" #nr "\n\t" \ "call "SYMBOL_NAME_STR(do_IRQ)"\n\t" \ "addl $8,%esp\n\t" \ "cli\n\t" \ UNBLK_##chip(mask) \ "decl "SYMBOL_NAME_STR(intr_count)"\n\t" \ "jmp ret_from_sys_call\n"); #endif #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/locks.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/locks.h?rev=1.1&content-type=text/x-cvsweb-markup Index: locks.h =================================================================== /* * SMP locks primitives for building ix86 locks * (not yet used). * * Alan Cox, alan@c..., 1995 */ /* * This would be much easier but far less clear and easy * to borrow for other processors if it was just assembler. */ extern __inline__ void prim_spin_lock(struct spinlock *sp) { int processor=smp_processor_id(); /* * Grab the lock bit */ while(lock_set_bit(0,&sp->lock)) { /* * Failed, but that's cos we own it! */ if(sp->cpu==processor) { sp->users++; return 0; } /* * Spin in the cache S state if possible */ while(sp->lock) { /* * Wait for any invalidates to go off */ if(smp_invalidate_needed&(1<<processor)) while(lock_clear_bit(processor,&smp_invalidate_needed)) local_flush_tlb(); sp->spins++; } /* * Someone wrote the line, we go 'I' and get * the cache entry. Now try to regrab */ } sp->users++;sp->cpu=processor; return 1; } /* * Release a spin lock */ extern __inline__ int prim_spin_unlock(struct spinlock *sp) { /* This is safe. The decrement is still guarded by the lock. A multilock would not be safe this way */ if(!--sp->users) { lock_clear_bit(0,&sp->lock);sp->cpu= NO_PROC_ID; return 1; } return 0; } /* * Non blocking lock grab */ extern __inline__ int prim_spin_lock_nb(struct spinlock *sp) { if(lock_set_bit(0,&sp->lock)) return 0; /* Locked already */ sp->users++; return 1; /* We got the lock */ } /* * These wrap the locking primitives up for usage */ extern __inline__ void spinlock(struct spinlock *sp) { if(sp->priority<current->lock_order) panic("lock order violation: %s (%d)\n", sp->name, current->lock_order); if(prim_spin_lock(sp)) { /* * We got a new lock. Update the priority chain */ sp->oldpri=current->lock_order; current->lock_order=sp->priority; } } extern __inline__ void spinunlock(struct spinlock *sp) { if(current->lock_order!=sp->priority) panic("lock release order violation %s (%d)\n", sp->name, current->lock_order); if(prim_spin_unlock(sp)) { /* * Update the debugging lock priority chain. We dumped * our last right to the lock. */ current->lock_order=sp->oldpri; } } extern __inline__ void spintestlock(struct spinlock *sp) { /* * We do no sanity checks, it's legal to optimistically * get a lower lock. */ prim_spin_lock_nb(sp); } extern __inline__ void spintestunlock(struct spinlock *sp) { /* * A testlock doesn't update the lock chain so we * must not update it on free */ prim_spin_unlock(sp); } 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/math_emu.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/math_emu.h?rev=1.1&content-type=text/x-cvsweb-markup Index: math_emu.h =================================================================== #ifndef _I386_MATH_EMU_H #define _I386_MATH_EMU_H #include <asm/sigcontext.h> void restore_i387_soft(struct _fpstate *buf); struct _fpstate * save_i387_soft(struct _fpstate * buf); struct fpu_reg { char sign; char tag; long exp; unsigned sigl; unsigned sigh; }; /* This structure matches the layout of the data saved to the stack following a device-not-present interrupt, part of it saved automatically by the 80386/80486. */ struct info { long ___orig_eip; long ___ret_from_system_call; long ___ebx; long ___ecx; long ___edx; long ___esi; long ___edi; long ___ebp; long ___eax; long ___ds; long ___es; long ___fs; long ___gs; long ___orig_eax; long ___eip; long ___cs; long ___eflags; long ___esp; long ___ss; long ___vm86_es; /* This and the following only in vm86 mode */ long ___vm86_ds; long ___vm86_fs; long ___vm86_gs; }; /* Interface for converting data between the emulator format * and the hardware format. Used for core dumping and for * ptrace(2) */ void hardreg_to_softreg(const char hardreg[10], struct fpu_reg *soft_reg); void softreg_to_hardreg(const struct fpu_reg *rp, char d[10], long int control_word); #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/mman.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/mman.h?rev=1.1&content-type=text/x-cvsweb-markup Index: mman.h =================================================================== #ifndef __I386_MMAN_H__ #define __I386_MMAN_H__ #define PROT_READ 0x1 /* page can be read */ #define PROT_WRITE 0x2 /* page can be written */ #define PROT_EXEC 0x4 /* page can be executed */ #define PROT_NONE 0x0 /* page can not be accessed */ #define MAP_SHARED 0x01 /* Share changes */ #define MAP_PRIVATE 0x02 /* Changes are private */ #define MAP_TYPE 0x0f /* Mask for type of mapping */ #define MAP_FIXED 0x10 /* Interpret addr exactly */ #define MAP_ANONYMOUS 0x20 /* don't use a file */ #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ #define MAP_EXECUTABLE 0x1000 /* mark it as a executable */ #define MAP_LOCKED 0x2000 /* pages are locked */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ #define MS_SYNC 4 /* synchronous memory sync */ #define MCL_CURRENT 1 /* lock all current mappings */ #define MCL_FUTURE 2 /* lock all future mappings */ /* compatibility flags */ #define MAP_ANON MAP_ANONYMOUS #define MAP_FILE 0 #endif /* __I386_MMAN_H__ */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/mmu_context.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/mmu_context.h?rev=1.1&content-type=text/x-cvsweb-markup Index: mmu_context.h =================================================================== #ifndef __I386_MMU_CONTEXT_H #define __I386_MMU_CONTEXT_H /* * get a new mmu context.. x86's don't know about contexts. */ #define get_mmu_context(x) do { } while (0) #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/mtrr.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/mtrr.h?rev=1.1&content-type=text/x-cvsweb-markup Index: mtrr.h =================================================================== /* Generic MTRR (Memory Type Range Register) ioctls. Copyright (C) 1997 Richard Gooch This library is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with this library; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Richard Gooch may be reached by email at rgooch@a... The postal address is: Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. modified by Mathias Fr"ohlich, Jan, 1998 <frohlich@n...> */ #ifndef _LINUX_MTRR_H #define _LINUX_MTRR_H /* These are the region types */ #define MTRR_TYPE_UNCACHABLE 0 #define MTRR_TYPE_WRCOMB 1 /*#define MTRR_TYPE_ 2*/ /*#define MTRR_TYPE_ 3*/ #define MTRR_TYPE_WRTHROUGH 4 #define MTRR_TYPE_WRPROT 5 #define MTRR_TYPE_WRBACK 6 #define MTRR_NUM_TYPES 7 static char *attrib_to_str (int x) __attribute__ ((unused)); static char *attrib_to_str (int x) { switch (x) { case 0: return "uncachable"; case 1: return "write-combining"; case 4: return "write-through"; case 5: return "write-protect"; case 6: return "write-back"; default: return "?"; } } /* End Function attrib_to_str */ #ifdef __KERNEL__ #ifdef CONFIG_MTRR extern void check_mtrr_config(void); extern void init_mtrr_config(void); /* extern void set_mtrr_config(void); */ #endif /* CONFIG_MTRR */ #endif /* __KERNEL__ */ #endif /* _LINUX_MTRR_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/page.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/page.h?rev=1.1&content-type=text/x-cvsweb-markup Index: page.h =================================================================== #ifndef _I386_PAGE_H #define _I386_PAGE_H /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 #define PAGE_SIZE (1UL << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #ifdef __KERNEL__ #ifndef __ASSEMBLY__ #define STRICT_MM_TYPECHECKS #ifdef STRICT_MM_TYPECHECKS /* * These are used to make use of C type-checking.. */ typedef struct { unsigned long pte; } pte_t; typedef struct { unsigned long pmd; } pmd_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #define pte_val(x) ((x).pte) #define pmd_val(x) ((x).pmd) #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) #define __pte(x) ((pte_t) { (x) } ) #define __pmd(x) ((pmd_t) { (x) } ) #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) #else /* * .. while these make it easier on the compiler */ typedef unsigned long pte_t; typedef unsigned long pmd_t; typedef unsigned long pgd_t; typedef unsigned long pgprot_t; #define pte_val(x) (x) #define pmd_val(x) (x) #define pgd_val(x) (x) #define pgprot_val(x) (x) #define __pte(x) (x) #define __pmd(x) (x) #define __pgd(x) (x) #define __pgprot(x) (x) #endif #endif /* !__ASSEMBLY__ */ /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) /* This handles the memory map.. */ #define __PAGE_OFFSET ((0x1000-CONFIG_MAX_MEMSIZE)<<20) #define PAGE_OFFSET (0) #define MAP_NR(addr) (((unsigned long)(addr)) >> PAGE_SHIFT) #endif /* __KERNEL__ */ #endif /* _I386_PAGE_H */ 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/param.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/param.h?rev=1.1&content-type=text/x-cvsweb-markup Index: param.h =================================================================== #ifndef _ASMi386_PARAM_H #define _ASMi386_PARAM_H #ifndef HZ #define HZ 100 #endif #define EXEC_PAGESIZE 4096 #ifndef NGROUPS #define NGROUPS 32 #endif #ifndef NOGROUP #define NOGROUP (-1) #endif #define MAXHOSTNAMELEN 64 /* max length of hostname */ #endif 1.1 or1k/rc203soc/sw/uClinux/include/asm-i386/pgtable.h http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/sw/uClinux/include/asm-i386/pgtable.h?rev=1.1&content-type=text/x-cvsweb-markup Index: pgtable.h =================================================================== #ifndef _I386_PGTABLE_H #define _I386_PGTABLE_H #include <linux/config.h> /* * Define USE_PENTIUM_MM if you want the 4MB page table optimizations. * This works only on a intel Pentium. */ #define USE_PENTIUM_MM 1 /* * The Linux memory management assumes a three-level page table setup. On * the i386, we use that, but "fold" the mid level into the top-level page * table, so that we physically have the same two-level page table as the * i386 mmu expects. * * This file contains the functions and defines necessary to modify and use * the i386 page table tree. */ #ifndef __ASSEMBLY__ /* Caches aren't brain-dead on the intel. */ #define flush_cache_all() do { } while (0) #define flush_cache_mm(mm) do { } while (0) #define flush_cache_range(mm, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) #define flush_page_to_ram(page) do { } while (0) #define flush_pages_to_ram(page,n) do { } while (0) /* * TLB flushing: * * - flush_tlb() flushes the current mm struct TLBs * - flush_tlb_all() flushes all processes TLBs * - flush_tlb_mm(mm) flushes the specified mm context TLB's * - flush_tlb_page(vma, vmaddr) flushes one page * - flush_tlb_range(mm, start, end) flushes a range of pages * * ..but the i386 has somewhat limited tlb flushing capabilities, * and page-granular flushes are available only on i486 and up. */ #define __flush_tlb() \ do { unsigned long tmpreg; __asm__ __volatile__("movl %%cr3,%0\n\tmovl %0,%%cr3":"=r" (tmpreg) : :"memory"); } while (0) /* * NOTE! The intel "invlpg" semantics are extremely strange. The * chip will add the segment base to the memory address, even though * no segment checking is done. We correct for this by using an * offset of -__PAGE_OFFSET that will wrap around the kernel segment base * of __PAGE_OFFSET to get the correct address (it will always be outside * the kernel segment, but we're only interested in the final linear * address. */ #define __invlpg_mem(addr) \ (*((char *)(addr)-__PAGE_OFFSET)) #define __invlpg(addr) \ __asm__ __volatile__("invlpg %0": :"m" (__invlpg_mem(addr))) /* * The i386 doesn't have a page-granular invalidate. Invalidate * everything for it. */ #ifdef CONFIG_M386 #define __flush_tlb_one(addr) __flush_tlb() #else #define __flush_tlb_one(addr) __invlpg(addr) #endif #ifndef __SMP__ #define flush_tlb() __flush_tlb() #define flush_tlb_all() __flush_tlb() #define local_flush_tlb() __flush_tlb() static inline void flush_tlb_mm(struct mm_struct *mm) { if (mm == current->mm) __flush_tlb(); } static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { if (vma->vm_mm == current->mm) __flush_tlb_one(addr); } static inline void flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) { if (mm == current->mm) __flush_tlb(); } #else /* * We aren't very clever about this yet - SMP could certainly * avoid some global flushes.. */ #include <asm/smp.h> #define local_flush_tlb() \ __flush_tlb() #define CLEVER_SMP_INVALIDATE #ifdef CLEVER_SMP_INVALIDATE