|
Message
From: cvs at opencores.org<cvs@o...>
Date: Tue Nov 29 16:46:05 CET 2005
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/05/11 29:16:46 Modified: jop/vhdl/memory mem_sc.vhd
Log:
removed signal mem_bsy
Revision Changes Path
1.3 jop/vhdl/memory/mem_sc.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/mem_sc.vhd.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_sc.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/memory/mem_sc.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- mem_sc.vhd 28 Nov 2005 18:41:31 -0000 1.2
+++ mem_sc.vhd 29 Nov 2005 15:46:04 -0000 1.3
@@ -114,8 +114,6 @@
signal mem_wr_addr : std_logic_vector(addr_bits-1 downto 0);
signal ram_addr : std_logic_vector(addr_bits-1 downto 0);
-
- signal mem_bsy : std_logic;
signal bcl_bsy : std_logic;
@@ -144,9 +142,7 @@
begin
- mem_bsy <= '1' when rdy_cnt=3 or bcl_bsy='1' else '0';
-
- bsy <= mem_bsy;
+ bsy <= '1' when rdy_cnt=3 or bcl_bsy='1' else '0';
bcstart <= std_logic_vector(to_unsigned(0, 32-jpc_width)) & cache_bcstart & "00";
|
 |
Browse
