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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Nov 28 19:42:17 CET 2005
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/05/11 28:19:42 Modified: jop/vhdl/core extension.vhd
Log:
Explicit exr data register after the data rd MUX
Revision Changes Path
1.6 jop/vhdl/core/extension.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/extension.vhd.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: extension.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/core/extension.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- extension.vhd 26 Jul 2005 12:06:05 -0000 1.5
+++ extension.vhd 28 Nov 2005 18:42:16 -0000 1.6
@@ -32,6 +32,7 @@
-- 2005-04-05 Reserve negative addresses for wishbone interface
-- 2005-04-07 generate bsy from delayed wr or'ed with mem_bsy
-- 2005-05-30 added wishbone interface
+-- 2005-11-28 add SimpCon IO interface
--
@@ -119,6 +120,8 @@
signal wr_dly : std_logic; -- generate a bsy with delayed wr
+ signal exr : std_logic_vector(31 downto 0); -- extension data register
+
--
-- Wishbone specific signals
--
@@ -138,29 +141,31 @@
mul_dout
);
+ dout <= exr;
+
--
-- read
--
process(clk, reset)
begin
if (reset='1') then
- dout <= (others => '0');
+ exr <= (others => '0');
io_rd <= '0';
elsif rising_edge(clk) then
- dout <= (others => '0');
+ exr <= (others => '0');
if (ext_addr="010") then
if rdaddr_msb='0' then
- dout <= mem_data;
+ exr <= mem_data;
else
- dout <= wb_data;
+ exr <= wb_data;
end if;
elsif (ext_addr="101") then
- dout <= mul_dout;
+ exr <= mul_dout;
elsif (ext_addr="111") then
- dout <= mem_bcstart;
+ exr <= mem_bcstart;
else
- dout <= io_data;
+ exr <= io_data;
end if;
io_rd <= '0';
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