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From: cvs at opencores.org<cvs@o...>
Date: Mon Nov 28 19:41:32 CET 2005
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/05/11 28:19:41

Modified: jop/vhdl/memory mem_sc.vhd sc_sram32.vhd
Log:
Changed signal names to use the names from the specification.


Revision Changes Path
1.2 jop/vhdl/memory/mem_sc.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/mem_sc.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: mem_sc.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/memory/mem_sc.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- mem_sc.vhd 24 Nov 2005 20:51:40 -0000 1.1
+++ mem_sc.vhd 28 Nov 2005 18:41:31 -0000 1.2
@@ -1,7 +1,9 @@
--
-- mem_sc.vhd
--
--- external memory interface with SimpCon
+-- External memory interface with SimpCon
+-- Translates between JOP/extension memory interface
+-- and SimpCon memory interface
--
--
-- todo:
@@ -42,11 +44,11 @@

-- SimpCon interface

- addr : out std_logic_vector(addr_bits-1 downto 0);
+ address : out std_logic_vector(addr_bits-1 downto 0);
wr_data : out std_logic_vector(31 downto 0);
rd, wr : out std_logic;
rd_data : in std_logic_vector(31 downto 0);
- bsy_cnt : in unsigned(1 downto 0)
+ rdy_cnt : in unsigned(1 downto 0)

);
end mem_sc;
@@ -142,7 +144,7 @@

begin

- mem_bsy <= '1' when bsy_cnt=3 or bcl_bsy='1' else '0';
+ mem_bsy <= '1' when rdy_cnt=3 or bcl_bsy='1' else '0';

bsy <= mem_bsy;

@@ -179,7 +181,7 @@
--


- addr <= ram_addr;
+ address <= ram_addr;
wr <= mem_wr;
rd <= mem_rd or bc_rd;
wr_data <= din;
@@ -246,7 +248,7 @@
--
-- next state logic
--
-process(state, mem_rd, mem_wr, mem_bc_rd, bsy_cnt,
+process(state, mem_rd, mem_wr, mem_bc_rd, rdy_cnt,
cache_rdy, cache_in_cache, bc_len)
begin

@@ -267,7 +269,7 @@
-- where the data is available
when rd1 =>
-- either 1 or 0
- if bsy_cnt(1)='0' then
+ if rdy_cnt(1)='0' then
next_state <= idl;
end if;

@@ -276,7 +278,7 @@
-- However, it is not used in JOP (at the moment).
when wr1 =>
-- either 1 or 0
- if bsy_cnt(1)='0' then
+ if rdy_cnt(1)='0' then
next_state <= idl;
end if;

@@ -306,11 +308,11 @@
if bc_len=to_unsigned(0, jpc_width-3) then
next_state <= bc_wl;
-- this works with pipeline level 1
- -- elsif bsy_cnt(1)='0' then
+ -- elsif rdy_cnt(1)='0' then

-- we need a pipeline level of 2 in
-- the memory interface for this to work!
- elsif bsy_cnt/=3 then
+ elsif rdy_cnt/=3 then next_state <= bc_rn; end if; @@ -324,7 +326,7 @@ when bc_wr => -- w. pipeline level 2 - if bsy_cnt/=3 then + if rdy_cnt/=3 then next_state <= bc_rn; else next_state <= bc_w; @@ -332,7 +334,7 @@ -- wait fot the last ack when bc_wl => - if bsy_cnt(1)='0' then + if rdy_cnt(1)='0' then next_state <= idl; end if; 1.2 jop/vhdl/memory/sc_sram32.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/sc_sram32.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: sc_sram32.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/memory/sc_sram32.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- sc_sram32.vhd 24 Nov 2005 20:51:40 -0000 1.1 +++ sc_sram32.vhd 28 Nov 2005 18:41:31 -0000 1.2 @@ -37,11 +37,11 @@ -- SimpCon interface - addr : in std_logic_vector(addr_bits-1 downto 0); + address : in std_logic_vector(addr_bits-1 downto 0); wr_data : in std_logic_vector(31 downto 0); rd, wr : in std_logic; rd_data : out std_logic_vector(31 downto 0); - bsy_cnt : out unsigned(1 downto 0); + rdy_cnt : out unsigned(1 downto 0); -- memory interface @@ -90,7 +90,7 @@ ram_dout_en <= dout_ena; - bsy_cnt <= cnt; + rdy_cnt <= cnt; -- -- Register memory address, write data and read data @@ -106,7 +106,7 @@ elsif rising_edge(clk) then if rd='1' or wr='1' then - ram_addr <= addr(17 downto 0); + ram_addr <= address(17 downto 0); end if; if wr='1' then ram_dout <= wr_data;