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From: cvs at opencores.org<cvs@o...>
Date: Mon Nov 28 19:13:51 CET 2005
Subject: [cvs-checkins] MODIFIED: simpcon ...
Date: 00/05/11 28:19:13

Modified: simpcon/vhdl sc_sram32.vhd
Log:
Changed signal names to use the names from the specification.


Revision Changes Path
1.2 simpcon/vhdl/sc_sram32.vhd

http://www.opencores.org/cvsweb.shtml/simpcon/vhdl/sc_sram32.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: sc_sram32.vhd
===================================================================
RCS file: /cvsroot/martin/simpcon/vhdl/sc_sram32.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- sc_sram32.vhd 28 Nov 2005 08:32:00 -0000 1.1
+++ sc_sram32.vhd 28 Nov 2005 18:13:50 -0000 1.2
@@ -37,11 +37,11 @@

-- SimpCon interface

- addr : in std_logic_vector(addr_bits-1 downto 0);
+ address : in std_logic_vector(addr_bits-1 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd, wr : in std_logic;
rd_data : out std_logic_vector(31 downto 0);
- bsy_cnt : out unsigned(1 downto 0);
+ rdy_cnt : out unsigned(1 downto 0);

-- memory interface

@@ -90,7 +90,7 @@

ram_dout_en <= dout_ena;

- bsy_cnt <= cnt;
+ rdy_cnt <= cnt;

--
-- Register memory address, write data and read data
@@ -106,7 +106,7 @@
elsif rising_edge(clk) then

if rd='1' or wr='1' then
- ram_addr <= addr(17 downto 0);
+ ram_addr <= address(17 downto 0);
end if;
if wr='1' then
ram_dout <= wr_data;