Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Thu Oct 27 19:20:53 CEST 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/10 27:19:20

Modified: or1k/rc203soc/rtl/verilog/rc203 rc203_zbtcontroller.v
Log:
Supports two RAM banks by Jacob Bower


Revision Changes Path
1.3 or1k/rc203soc/rtl/verilog/rc203/rc203_zbtcontroller.v

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/rtl/verilog/rc203/rc203_zbtcontroller.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: rc203_zbtcontroller.v
===================================================================
RCS file: /cvsroot/jcastillo/or1k/rc203soc/rtl/verilog/rc203/rc203_zbtcontroller.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- rc203_zbtcontroller.v 16 Sep 2005 00:39:04 -0000 1.2
+++ rc203_zbtcontroller.v 27 Oct 2005 17:20:52 -0000 1.3
@@ -42,6 +42,9 @@
// CVS Revision History
//
// $Log: rc203_zbtcontroller.v,v $
+// Revision 1.3 2005/10/27 17:20:52 jcastillo
+// Supports two RAM banks by Jacob Bower
+//
// Revision 1.2 2005/09/16 00:39:04 jcastillo
// no message
//
@@ -59,8 +62,13 @@
wb_ack_o,wb_adr_i,wb_we_i,
wb_cyc_i,wb_sel_i,

- nRW,address,data,
- nBW,nCS
+ // Bank 0
+ nRW0,address0,data0,
+ nBW0,nCS0,
+
+ // Bank 1
+ nRW1,address1,data1,
+ nBW1,nCS1
);

input clk;
@@ -78,30 +86,50 @@
input [3:0] wb_sel_i;

//
-// RAM PINS
+// RAM PINS Bank 0
//
-output nRW;
-output [19:0] address;
-inout [31:0] data; //INOUT
-output [3:0] nBW;
-output nCS;
+output nRW0;
+output [19:0] address0;
+inout [31:0] data0; //INOUT
+output [3:0] nBW0;
+output nCS0;
+
+//
+// RAM PINS Bank 1
+//
+output nRW1;
+output [19:0] address1;
+inout [31:0] data1; //INOUT
+output [3:0] nBW1;
+output nCS1;

reg [31:0] wb_dat_o;
reg wb_ack_o;
-reg nRW;
-reg [19:0] address;
-reg [3:0] nBW;
-wire [31:0] data;
-wire nCS;

+reg nRW0;
+reg [19:0] address0;
+reg [3:0] nBW0;
+wire [31:0] data0;
+wire nCS0;
+
+reg nRW1;
+reg [19:0] address1;
+reg [3:0] nBW1;
+wire [31:0] data1;
+wire nCS1;
+
+reg next_bank_select;
+reg bank_select;
reg next_reading;
reg reading;
reg next_writing;
reg writing;

-assign nCS = 1'b0; +assign nCS0 = 1'b0; +assign nCS1 = 1'b0; -assign data = writing ? wb_dat_i : 32'hZ; +assign data0 = (writing && !bank_select) ? wb_dat_i : 32'hZ; +assign data1 = (writing && bank_select) ? wb_dat_i : 32'hZ; //read_data: always @(posedge clk or posedge reset) @@ -118,7 +146,10 @@ if (reading) begin wb_ack_o <= #1 1'b1; - wb_dat_o <= #1 data; + if(bank_select== 1) + wb_dat_o <= #1 data1; + else + wb_dat_o <= #1 data0; end else if(writing) begin @@ -140,41 +171,38 @@ addr_var = wb_adr_i ; addr_var = addr_var>>2; - address = addr_var[19:0]; + address0 = addr_var[20:1]; + address1 = addr_var[20:1]; - nRW = 1; + // We select bank using low bits so people with + // non-expert versions of the rc20x boards can + // use both RAM banks without changing any RTL. + next_bank_select = addr_var[0]; - nBW = ~wb_sel_i ; + nRW0 = 1; + nRW1 = 1; + + nBW0 = ~wb_sel_i ; + nBW1 = ~wb_sel_i ; if(~reading && ~writing && ~wb_ack_o) begin if (wb_cyc_i && wb_stb_i && !wb_we_i) begin -// Single memory read - addr_var = wb_adr_i ; - addr_var = addr_var>>2; - address = addr_var[19:0]; - nRW = 1'b1; + // Single memory read next_reading = 1'b1; end else if (wb_cyc_i && wb_stb_i && wb_we_i) begin -// Single memory write - addr_var = wb_adr_i ; - addr_var = addr_var >> 2; - address = addr_var[19:0]; + // Single memory write + if(next_bank_select == 1) + nRW1 = 0; + else + nRW0 = 0; next_writing = 1'b1; - nRW = 0; end end - if(reading) - next_reading=1'b0; - if(writing) - begin - next_writing=1'b0; - nRW=1; - end end @@ -190,6 +218,7 @@ end else begin + bank_select <= #1 next_bank_select; writing <= #1 next_writing; reading <= #1 next_reading; end