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From: cvs at opencores.org<cvs@o...>
Date: Thu Oct 27 19:20:51 CEST 2005
Subject: [cvs-checkins] MODIFIED: or1k ...
Date: 00/05/10 27:19:20

Modified: or1k/rc203soc/rtl/verilog soc.v
Log:
Supports two RAM banks by Jacob Bower


Revision Changes Path
1.4 or1k/rc203soc/rtl/verilog/soc.v

http://www.opencores.org/cvsweb.shtml/or1k/rc203soc/rtl/verilog/soc.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: soc.v
===================================================================
RCS file: /cvsroot/jcastillo/or1k/rc203soc/rtl/verilog/soc.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- soc.v 16 Sep 2005 00:39:03 -0000 1.3
+++ soc.v 27 Oct 2005 17:20:50 -0000 1.4
@@ -43,6 +43,9 @@
// CVS Revision History
//
// $Log: soc.v,v $
+// Revision 1.4 2005/10/27 17:20:50 jcastillo
+// Supports two RAM banks by Jacob Bower
+//
// Revision 1.3 2005/09/16 00:39:03 jcastillo
// no message
//
@@ -82,8 +85,11 @@
clk,reset,

//SRAM Ports
- sram_nRW,sram_clk,sram_address,
- sram_data,sram_nBW,sram_nCS,
+ sram_nRW0,sram_clk0,sram_address0,
+ sram_data0,sram_nBW0,sram_nCS0,
+
+ sram_nRW1,sram_clk1,sram_address1,
+ sram_data1,sram_nBW1,sram_nCS1,

//UART ports
uart_stx,uart_srx,
@@ -106,12 +112,19 @@
input clk /* synthesis xc_clockbuftype = "BUFGDLL" */;
input reset;

- output sram_nRW;
- output [19:0] sram_address;
- inout [31:0] sram_data;
- output [3:0] sram_nBW;
- output sram_nCS;
- output sram_clk;
+ output sram_nRW0;
+ output [19:0] sram_address0;
+ inout [31:0] sram_data0;
+ output [3:0] sram_nBW0;
+ output sram_nCS0;
+ output sram_clk0;
+
+ output sram_nRW1;
+ output [19:0] sram_address1;
+ inout [31:0] sram_data1;
+ output [3:0] sram_nBW1;
+ output sram_nCS1;
+ output sram_clk1;

output uart_stx;
input uart_srx;
@@ -131,7 +144,8 @@
output [1:0] eth_nBE;
output eth_reset;

-assign sram_clk=clk;
+assign sram_clk0=clk;
+assign sram_clk1=clk;

//Declaring signals
wire [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
@@ -708,11 +722,17 @@
.wb_cyc_i ( sram_wb_cyc ),
.wb_sel_i ( sram_wb_sel ),

- .nRW ( sram_nRW ),
- .address ( sram_address ),
- .data ( sram_data ),
- .nBW ( sram_nBW ),
- .nCS ( sram_nCS )
+ .nRW0 ( sram_nRW0 ),
+ .address0 ( sram_address0 ),
+ .data0 ( sram_data0 ),
+ .nBW0 ( sram_nBW0 ),
+ .nCS0 ( sram_nCS0 ),
+
+ .nRW1 ( sram_nRW1 ),
+ .address1 ( sram_address1 ),
+ .data1 ( sram_data1 ),
+ .nBW1 ( sram_nBW1 ),
+ .nCS1 ( sram_nCS1 )
); //