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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: OpenCores CVS Agent<cvs@o...>
    Date: Wed Jan 26 19:55:48 CET 2005
    Subject: [cvs-checkins] MODIFIED: tv80 ...
    Top
    Date: 00/05/01 26:19:55

    Modified: tv80/rtl/core tv80_core.v tv80s.v
    Log:
    Added ifdef TV80_REFRESH, to remove refresh logic by default. Also

    ran untabify to remove tabs from source code.




    Revision Changes Path
    1.5 +630 -623 tv80/rtl/core/tv80_core.v

    http://www.opencores.org/cvsweb.shtml/tv80/rtl/core/tv80_core.v.diff?r1=1.4&r2=1.5

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: tv80_core.v
    ===================================================================
    RCS file: /cvsroot/ghutchis/tv80/rtl/core/tv80_core.v,v
    retrieving revision 1.4
    retrieving revision 1.5
    diff -u -b -r1.4 -r1.5
    --- tv80_core.v 5 Oct 2004 08:09:43 -0000 1.4
    +++ tv80_core.v 26 Jan 2005 18:55:47 -0000 1.5
    @@ -369,7 +369,9 @@
    Ap <= #1 8'hFF;
    Fp <= #1 8'hFF;
    I <= #1 0;
    + `ifdef TV80_REFRESH
    R <= #1 0;
    + `endif
    SP <= #1 16'hFFFF;
    Alternate <= #1 1'b0;

    @@ -413,16 +415,16 @@
    if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] ))
    begin
    // mcycle == 1 && tstate == 1, 2, || 3
    -
    if (tstate[2] && wait_n == 1'b1 )
    begin
    + `ifdef TV80_REFRESH
    if (Mode < 2 )
    begin
    A[7:0] <= #1 R;
    A[15:8] <= #1 I;
    R[6:0] <= #1 R[6:0] + 1;
    end
    -
    + `endif
    if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) )
    begin
    PC <= #1 PC16;
    @@ -726,8 +728,12 @@
    2'b10 :
    I <= #1 ACC;

    + `ifdef TV80_REFRESH
    default :
    R <= #1 ACC;
    + `else
    + default : ;
    + `endif
    endcase
    end
    end // if (tstate == 3 )
    @@ -1067,6 +1073,7 @@
    // Generate external control signals
    //
    //-------------------------------------------------------------------------
    +`ifdef TV80_REFRESH
    always @ (posedge clk)
    begin
    if (reset_n == 1'b0 )
    @@ -1088,7 +1095,7 @@
    end
    end
    end
    -
    +`endif

    always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
    or IntE_FF1 or di or iorq_i or mcycle or tstate)
    @@ -1341,7 +1348,7 @@
    end // always @ *

    // synopsys dc_script_begin
    -// set_attribute current_design "revision" "$Id: tv80_core.v,v 1.4 2004/10/05 08:09:43 ghutchis Exp $" -type string -quiet
    +// set_attribute current_design "revision" "$Id: tv80_core.v,v 1.5 2005/01/26 18:55:47 ghutchis Exp $" -type string -quiet
    // synopsys dc_script_end
    endmodule // T80




    1.4 +41 -39 tv80/rtl/core/tv80s.v

    http://www.opencores.org/cvsweb.shtml/tv80/rtl/core/tv80s.v.diff?r1=1.3&r2=1.4

    (In the diff below, changes in quantity of whitespace are not shown.)
    Index: tv80s.v =================================================================== RCS file: /cvsroot/ghutchis/tv80/rtl/core/tv80s.v,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- tv80s.v 5 Oct 2004 08:09:43 -0000 1.3 +++ tv80s.v 26 Jan 2005 18:55:47 -0000 1.4 @@ -119,8 +119,10 @@ mreq_n <= #1 ~ intcycle_n; iorq_n <= #1 intcycle_n; end + `ifdef TV80_REFRESH if (tstate[3]) mreq_n <= #1 1'b0; + `endif end // if (mcycle[0]) else begin

     
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