Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: OpenCores CVS Agent<cvs@w...>
Date: Mon Apr 26 17:26:25 CEST 2004
Subject: [cvs-checkins] ethernet/rtl/verilog eth_registers.v eth_rxeth ...
CVSROOT: /home/oc/cvs
Module name: ethernet
Changes by: igorm 04/04/26 17:26:24

Modified files:
rtl/verilog : eth_registers.v eth_rxethmac.v eth_top.v
eth_wishbone.v

Log message:
- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries