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From: OpenCores CVS Agent<cvs@w...>
Date: Sat Mar 27 05:09:31 CET 2004
Subject: [cvs-checkins] uart16550/sim/rtl_sim/log uart_interrupts_repo ...
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: tadejm 04/03/27 05:09:26

Added files:
sim/rtl_sim/log: uart_interrupts_report.log
uart_interrupts_verbose.log

Log message:
Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.