|
Message
From: OpenCores CVS Agent<cvs@w...>
Date: Sat Mar 27 05:07:52 CET 2004
Subject: [cvs-checkins] uart16550/sim/rtl_sim/run run_sim.scr
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: tadejm 04/03/27 05:07:51
Added files:
sim/rtl_sim/run: run_sim.scr
Log message:
Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.
|
 |
Browse
