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Message
From: OpenCores CVS Agent<cvs@w...>
Date: Sat Mar 27 05:05:00 CET 2004
Subject: [cvs-checkins] uart16550/bench/verilog/test_cases uart_int.v
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: tadejm 04/03/27 05:04:59
Added files:
bench/verilog/test_cases: uart_int.v
Log message:
Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.
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