LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent<cvs@w...>
    Date: Thu Mar 25 23:29:23 CET 2004
    Subject: [cvs-checkins] Import
    Top
    CVSROOT: /cvsroot/arniml
    Module name: t48
    Changes by: arniml 04/03/25 23:29:22

    Log message:
    Imported sources

    Status:

    Vendor Tag: local
    Release Tags: transfer

    N t48/sw/verif/black_box/mov/ind_rr/test.asm
    N t48/sw/verif/black_box/mov/a_rr/data_00/test.asm
    N t48/sw/verif/black_box/mov/a_rr/data_num/test.asm
    N t48/sw/verif/black_box/mov/mov_rr_a/data_00/test.asm
    N t48/sw/verif/black_box/mov/mov_rr_a/data_num/test.asm
    N t48/sw/verif/black_box/jbb/jbb_all_1/test.asm
    N t48/sw/verif/black_box/jbb/jbb_all_0/test.asm
    N t48/sw/verif/black_box/jbb/jbb_aa/test.asm
    N t48/sw/verif/black_box/jbb/jbb_55/test.asm
    N t48/sw/verif/black_box/jmp/test.asm
    N t48/sw/verif/black_box/jz/test.asm
    N t48/sw/verif/black_box/jnz/test.asm
    N t48/sw/verif/black_box/add/a_data/test.asm
    N t48/sw/verif/black_box/add/rr/test.asm
    N t48/sw/verif/black_box/add/ind_rr/test.asm
    N t48/sw/verif/black_box/inc/rr/test.asm
    N t48/sw/verif/black_box/inc/a/test.asm
    N t48/sw/verif/black_box/inc/ind_rr/test.asm
    N t48/sw/verif/black_box/djnz/test.asm
    N t48/sw/verif/black_box/dec/a/test.asm
    N t48/sw/verif/black_box/dec/rr/test.asm
    N t48/sw/verif/black_box/clr/a/test.asm
    N t48/sw/verif/black_box/clr/f1/test.asm
    N t48/sw/verif/black_box/clr/c/test.asm
    N t48/sw/verif/black_box/clr/f0/test.asm
    N t48/sw/verif/black_box/cpl/a/test.asm
    N t48/sw/verif/black_box/cpl/f1/test.asm
    N t48/sw/verif/black_box/cpl/c/test.asm
    N t48/sw/verif/black_box/cpl/f0/test.asm
    N t48/sw/verif/black_box/swap/test.asm
    N t48/sw/verif/black_box/jc/test.asm
    N t48/sw/verif/black_box/jnc/test.asm
    N t48/sw/verif/black_box/anl/a_data/test.asm
    N t48/sw/verif/black_box/anl/rr/test.asm
    N t48/sw/verif/black_box/anl/ind_rr/test.asm
    N t48/sw/verif/black_box/anl/pp/test.asm
    N t48/sw/verif/black_box/anl/bus/test.asm
    N t48/sw/verif/black_box/addc/a_data/test.asm
    N t48/sw/verif/black_box/addc/rr/test.asm
    N t48/sw/verif/black_box/addc/ind_rr/test.asm
    N t48/sw/verif/black_box/psw/test.asm
    N t48/sw/verif/black_box/call/simple/test.asm
    N t48/sw/verif/black_box/call/call_ret/test.asm
    N t48/sw/verif/black_box/int/jni/test.asm
    N t48/sw/verif/black_box/int/simple_jump_to/test.asm
    N t48/sw/verif/black_box/int/simple_int_retr/test.asm
    N t48/sw/verif/black_box/jmpp/test.asm
    N t48/sw/verif/black_box/outl/pp/test.asm
    N t48/sw/verif/black_box/outl/bus/test.asm
    N t48/sw/verif/black_box/in/test.asm
    N t48/sw/verif/black_box/tx/t0/ent0_clk/test.asm
    N t48/sw/verif/black_box/tx/t0/t0/test.asm
    N t48/sw/verif/black_box/tx/t1/test.asm
    N t48/sw/verif/black_box/orl/pp/test.asm
    N t48/sw/verif/black_box/orl/a_data/test.asm
    N t48/sw/verif/black_box/orl/rr/test.asm
    N t48/sw/verif/black_box/orl/ind_rr/test.asm
    N t48/sw/verif/black_box/orl/bus/test.asm
    N t48/sw/verif/black_box/movp/test.asm
    N t48/sw/verif/black_box/xrl/a_data/test.asm
    N t48/sw/verif/black_box/xrl/rr/test.asm
    N t48/sw/verif/black_box/xrl/ind_rr/test.asm
    N t48/sw/verif/black_box/xch/rr/test.asm
    N t48/sw/verif/black_box/xch/ind_rr/test.asm
    N t48/sw/verif/black_box/rl/test.asm
    N t48/sw/verif/black_box/rc/test.asm
    N t48/sw/verif/black_box/movx/test.asm
    N t48/sw/verif/black_box/tim/t/test.asm
    N t48/sw/verif/black_box/tim/int/test.asm
    N t48/sw/verif/black_box/ins/test.asm
    N t48/sw/verif/black_box/rb/misc/test.asm
    N t48/sw/verif/black_box/rb/int/test.asm
    N t48/sw/verif/black_box/mb/call_jmp/test.asm
    N t48/sw/verif/black_box/mb/int/test.asm
    N t48/sw/verif/include/pass_fail.inc
    N t48/sw/verif/include/cpu.inc

    No conflicts created by this import

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.