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Message
From: OpenCores CVS Agent<cvs@w...>
Date: Thu Jan 22 14:58:57 CET 2004
Subject: [cvs-checkins] dbg_interface/ ench/verilog/dbg_tb.v tl/verilo ...
CVSROOT: /home/oc/cvs
Module name: dbg_interface
Changes by: mohor 04/01/22 14:58:54
Modified files:
bench/verilog : dbg_tb.v
rtl/verilog : dbg_cpu.v dbg_wb.v
Log message:
Port signals are all set to zero after reset.
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