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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Thu, 20 Nov 2003 06:08:10 +0100
Subject: [cvs-checkins] wb_tk/ /technology.vhd /wb_arbiter.vhd /wb_asy ...
CVSROOT: /home/oc/cvs
Module name: wb_tk
Changes by: tantos 03/11/20 06:08:09
Modified files:
. : technology.vhd wb_arbiter.vhd
wb_async_master.vhd wb_async_slave.vhd
wb_bus_dnsize.vhd wb_bus_resize.vhd
wb_bus_upsize.vhd wb_out_reg.vhd wb_ram.vhd
wb_test.vhd
Added files:
. : components.vhd technology_altera.vhd
technology_behav.vhd technology_xilinx.vhd
wb_in_reg.vhd
TestBench : wb_async_master_TB.vhd
Removed files:
. : Makefile compile.sh wb_tk.vhd
TestBench : wb_bus_dnsize_TB.vhd wb_out_reg_TB.vhd
Log message:
Large update to new version of wb_tk. Major changes:
- Xilinx support added
- Altera support is poor: though it's there I haven't tested or even compiled it for quite some time
- Behavioral models are added
- Async master is completely new: it's much more complicated but actually works
- Cores are tested in real HW (x2s300e)
- wb_out_reg currently lacks byte-select support
- wb_in_reg is added as a trivial input register
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