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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 12 Nov 2003 19:25:20 +0100
Subject: [cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_registe ...
CVSROOT: /home/oc/cvs
Module name: ethernet
Changes by: tadejm 03/11/12 19:25:20
Modified files:
rtl/verilog : eth_defines.v eth_registers.v
eth_spram_256x32.v eth_top.v eth_wishbone.v
Log message:
WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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