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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Fri, 24 Oct 2003 11:35:43 +0200
Subject: [cvs-checkins] pci/ tl/verilog/pci_wb_master.v im/rtl_sim/bin ...
CVSROOT: /home/oc/cvs
Module name: pci
Changes by: tadejm 03/10/24 11:35:42
Modified files:
rtl/verilog : pci_wb_master.v
sim/rtl_sim/bin: rtl_file_list.lst
sim/rtl_sim/run: ncvlog.args
Log message:
Added missing signals to 2 sensitivity lists. Everything works the same as before.
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