Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: OpenCores CVS Agent <cvs@w...>
Date: Sun, 12 Oct 2003 18:50:31 +0200
Subject: [cvs-checkins] c16/vhdl BaudGen.vhd bin_to_7segment.vhd board ...

CVSROOT:	/home/oc/cvs
Module name:	c16
Changes by:	jsauermann	03/10/12 18:50:30

Modified files:
	vhdl           : BaudGen.vhd bin_to_7segment.vhd board_cpu.bit 
	                 Board_cpu.vhd cpu.vhd cpu16.npl cpu_engine.vhd 
	                 cpu_pack.vhd cpu_test.vhd data_core.vhd 
	                 ds1722.vhd input_output.vhd mem_content.vhd 
	                 opcode_decoder.vhd opcode_fetch.vhd 
	                 select_yy.vhd temperature.vhd test.vhd 
	                 uart._baudgen.vhd uart.vhd uart_rx.vhd 
	                 uart_tx.vhd 

Log message:
	Made cpu_engine WISHBONE compliant.
	(Somebody please validate it).