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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 8 Oct 2003 11:38:33 +0200
Subject: [cvs-checkins] camera/rtl/verilog camera_wb_if.v
CVSROOT: /home/oc/cvs
Module name: camera
Changes by: tadejm 03/10/08 11:38:32
Modified files:
rtl/verilog : camera_wb_if.v
Log message:
One signal changed from wire to reg so that it's value can be forced from SoC testbench.
Solved bug in WB B3 state machine; unnecessary conditions deleted in end_burst state.
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