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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 1 Oct 2003 15:35:04 +0200
Subject: [cvs-checkins] camera/ ench/verilog/camera_bench_top.v tl/ver ...
CVSROOT: /home/oc/cvs
Module name: camera
Changes by: tadejm 03/10/01 15:35:04
Modified files:
bench/verilog : camera_bench_top.v
rtl/verilog : camera_cb_table.v camera_cr_table.v
camera_defines.v camera_fifo.v
camera_fifo_ctrl.v camera_io_calc.v
camera_sync_ctrl.v camera_top.v camera_tpram.v
camera_wb_if.v camera_y_table.v
sim/rtl_sim/bin: rtl_file_list.lst
sim/rtl_sim/log: ncelab_xilinx.log ncsim.log ncvlog.log
sim/rtl_sim/run: ncvlog.args top_groups.do
Log message:
Totaly new version. Supports BYPASS, input data ordering, output data ordering, interrupts after adjustable number of lines, INT_STATUS register, etc.
Currently there are problems with INT signal.
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