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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Tue, 30 Sep 2003 22:54:01 +0200
Subject: [cvs-checkins] can/ ench/verilog/can_testbench.v ench/verilog ...
CVSROOT: /home/oc/cvs
Module name: can
Changes by: mohor 03/09/30 22:54:01
Modified files:
bench/verilog : can_testbench.v can_testbench_defines.v
sim/rtl_sim/bin: memory_file_list
sim/rtl_sim/run: wave.do
syn/synplicity : can.prj
Log message:
Fixing the core to be Bosch VHDL Reference compatible.
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