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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Fri, 12 Sep 2003 09:23:43 +0200
Subject: [cvs-checkins] or1k/orp/orp_soc/rtl/verilog xsv_fpga_top.v
CVSROOT: /home/oc/cvs
Module name: or1k
Changes by: dries 03/09/12 09:23:42
Modified files:
orp/orp_soc/rtl/verilog: xsv_fpga_top.v
Log message:
disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
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