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From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 20 Aug 2003 12:03:57 +0200
Subject: [cvs-checkins] can/ ench/verilog/can_testbench.v im/rtl_sim/b ...

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/08/20 12:03:57

Modified files:
	bench/verilog  : can_testbench.v 
	sim/rtl_sim/bin: memory_file_list 
	sim/rtl_sim/run: run_sim.scr 

Log message:
	Artisan RAMs added.