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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: OpenCores CVS Agent <cvs@w...>
    Date: Wed, 11 Jun 2003 15:38:07 -0100
    Subject: [cvs-checkins] uart16550/rtl/verilog uart_defines.v uart_regs ...
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    CVSROOT:	/home/oc/cvs
    Module name:	uart16550
    Changes by:	gorban	03/06/11 15:38:06
    
    Modified files:
    	rtl/verilog    : uart_defines.v uart_regs.v uart_rfifo.v 
    
    Log message:
    	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
    
    
    
    
     
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