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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Mon, 26 May 2003 09:57:16 -0100
Subject: [cvs-checkins] spi/rtl/verilog spi_top.v
CVSROOT: /home/oc/cvs
Module name: spi
Changes by: simons 03/05/26 09:57:13
Modified files:
rtl/verilog : spi_top.v
Log message:
Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.
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