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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Mon, 7 Apr 2003 20:05:59 -0100
Subject: [cvs-checkins] or1k/orp/orp_soc/rtl/verilog xsv_fpga_top.v
CVSROOT: /home/oc/cvs
Module name: or1k
Changes by: lampret 03/04/07 20:05:59
Modified files:
orp/orp_soc/rtl/verilog: xsv_fpga_top.v
Log message:
WB = 1/2 RISC clock test code enabled.
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