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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 19 Mar 2003 11:50:56 -0100
Subject: [cvs-checkins] vga_lcd/rtl/verilog vga_vtim.v vga_wb_master.v ...
CVSROOT: /home/oc/cvs
Module name: vga_lcd
Changes by: rherveille 03/03/19 11:50:55
Modified files:
rtl/verilog : vga_vtim.v vga_wb_master.v
Removed files:
rtl/verilog : ro_cnt.v ud_cnt.v
Log message:
Changed timing generator; made it smaller and easier.
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