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Message
From: OpenCores CVS Agent <cvs-checkins-agent@o...>
Date: Sat, 20 Apr 2002 12:02:41 +0200
Subject: [cvs-checkins] vga_lcd/rtl/verilog vga_wb_slave.v vga_wb_mast ...
CVSROOT: /home/oc/cvs
Module name: vga_lcd
Changes by: rherveille 02/04/20 12:02:40
Modified files:
rtl/verilog : vga_wb_slave.v vga_wb_master.v vga_vtim.v
Log message:
Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).
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