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Message
From: Howard Harte<opencores@d...>
Date: Wed Feb 27 07:11:05 CET 2008
Subject: [oc] Re: PCI core question
I tried the latest version of the pci32tlite core on the formerly
problematic Dell P3 system and it works great. I also started more
rigorous testing on other systems, and it looks very good.
Thanks for the help.
Also the new generics in the pci32tlite core make configuration easy.
-Howard
On Feb 16, 2008, at 5:00 PM, Howard Harte <opencores@d...>
wrote:
> I'm using the OpenCores PCI core in a Spartan3 FPGA. It works very
> well, and I haven't run into any compatibility issues with any of
> the PC's I've tried it with, and I wrote drivers for it for Windows
> XP (using KMDF) and Linux.
>
> I'd be happy to contribute those to OpenCores if there is interest.
>
> One issue I'd like some advice on is improving read latency. For
> single 32-bit writes, they complete in about 300ns, which is fine.
> For 32-bit reads, they complete in 2.5uS, which is a really long
> time. I'm reading and writing to a FIFO, which occupies a single
> address on the wishbone backplane.
>
> Some things I've thought about are mapping the FIFO to a separate
> BAR, ignoring the lower address bits, and enabling read prefetching,
> but figured this might be dangerous since it's a FIFO.
>
> Another thing I considered is doing bus mastering to empty the FIFO
> into main memory, but this is a large change to my design.
>
> Any other thoughts on how to proceed?
>
> I tried the pci32tlite core, and it worked ok in some systems, but I
> ran into compatibility issues on a Dell Optiplex 700mhz P3 system so
> I switched over to the larger OC PCI core.
>
> In my design, the wishbone and PCI are operating from the 33MHz PCI
> clock.
>
> Thanks,
>
> -Howard
>
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