OPENCORES.ORG

Hello Howard,
I don't have any compatibility issue reported for the last revision of the pci32tlite IP core.
In the first revisión, back-to-back and burst cycles were not supported. It produced hangs on systems using this kind of cycles. Anyway, I'll be grateful if you share you experiences about the pci32tlite IP core. 

Peio

-----Mensaje original-----
De: cores-bounces@o... [mailto:cores-bounces@o...]En
nombre de Howard Harte
Enviado el: domingo, 17 de febrero de 2008 2:00
Para: cores@o...
Asunto: [oc] PCI core question

I'm using the OpenCores PCI core in a Spartan3 FPGA.  It works very  
well, and I haven't run into any compatibility issues with any of the  
PC's I've tried it with, and I wrote drivers for it for Windows XP  
(using KMDF) and Linux.

I'd be happy to contribute those to OpenCores if there is interest.

One issue I'd like some advice on is improving read latency.  For  
single 32-bit writes, they complete in about 300ns, which is fine.   
For 32-bit reads, they complete in 2.5uS, which is a really long  
time.  I'm reading and writing to a FIFO, which occupies a single  
address on the wishbone backplane.

Some things I've thought about are mapping the FIFO to a separate BAR,  
ignoring the lower address bits, and enabling read prefetching, but  
figured this might be dangerous since it's a FIFO.

Another thing I considered is doing bus mastering to empty the FIFO  
into main memory, but this is a large change to my design.

Any other thoughts on how to proceed?

I tried the pci32tlite core, and it worked ok in some systems, but I  
ran into compatibility issues on a Dell Optiplex 700mhz P3 system so I  
switched over to the larger OC PCI core.

In my design, the wishbone and PCI are operating from the 33MHz PCI  
clock.

Thanks,

-Howard

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores