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From: zuolin2005 at hotmail.com<zuolin2005@h...>
Date: Mon Feb 18 10:32:56 CET 2008
Subject: [oc] Some problems with wishbone simulation
hi,

when I was compiling the test.v file, which located in / wb_conmax /
bench, with ModelSim 6.3c, it always reported a error " Global
declarations are illegal in Verilog 2001 syntax." I have changed
syntax to Verilog 1995, it still had this problem........

Thanks