OPENCORES.ORG

I can't advise you on your toolset and target FPGA questions since mine are
different, however you will need to make the SDA pin bidirectional.  If the
FPGA is the only master, you can get away with SCL as output only, but in
general you should also make it bidirectional or at least tri-state to allow
other I2C masters.  You generally have to do this in the FPGA vendor's P&R
constraint file since specifying or inferring the pin types in the source
doesn't always get properly forwarded by the synthesis tool for various
reasons.

I recommend you download version 3.0 of the I2C spec from
http://www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf, which
contains recommendations for pullup resistor values as well as series
resistors and slope control.  You can also search for I2C at the NXP site to
find relevant app notes, forums, datasheets, and reference designs.  Note
that the pullup resistor value depends both on the I2C bus mode (standard,
fast, fast-plus) as well as the bus capacitance.  In general, you shouldn't
have less than a 10k pullup for standard mode, with 4.7k or even 2.2k a
better choice for fast mode or longer, loaded I2C buses.  Although the FPGA
probably has pullups, these are generally weak with a value of 50k or more
to minimize FPGA bank supply current requirements and heat dissipation.

The above are only suggestions and opinions, as my I2C experience has been
with different hardware and toolsets.

Tom Taylor
ttaylor_at_nospam_ateng.com

Thomas Winkler-4 wrote:
> 
> Hello,
> 
> I'm currently working on connecting the opencores I2C master (VHDL
> version) to 
> the NIOS 2 processor via the Avalon bus. I intend to run the NIOS 2 on the 
> Altera DE2 board (based on a Cyclone 2 FPGA).
> 
> So far I've completed the following step:
> 
> 1) Wrapper code that implements the tri-state buffers for SCL and SDA and 
> eliminates ARST_LVL and arst_i at the toplevel (I've tied ARST_LVL to '0'
> and 
> arst_i to '1').
> I've uploaded the source to 
> http://www.wnk.at/tmp/i2c/i2c_master_top_avalon.vhd
> 
> BTW: In the I2C master document there seems to be a mistake regarding the 
> tri-state: I think the last line should be sda_pad_i <= sda;  instead of 
> scl_pad_i <= sda;" 
> 
> 
> 2) I've create a SOPC component. The singals and itnerfaces of the SOPC 
> component can be found at
> http://www.wnk.at/tmp/i2c/sopc_signals.png
> and
> http://www.wnk.at/tmp/i2c/sopc_interfaces.png
> 
> I tried to stick to the information from the OC I2C FAQ. But I'm by no
> means 
> an SOPC or Avalon expert - so I'd be glad if someone with more experience 
> could have a brief look at it to tell me if it looks ok.
> 
> 
> 3) I've attached the I2C component to a simple NIOS 2 processor using SOPC 
> builder (see http://www.wnk.at/tmp/i2c/sopc_nios.png). After generating
> the 
> system I did a pin assignment in the Quartus II software. I assigned SCL
> and 
> SDA to pins of the expansion header of the DE2 board.
> What kind of surprised me was that SCL and SDA are recongized as pure
> output 
> pins by quartus although they are marked as bidirectional in SOPC builder.
> The pin assignment can be seen at:
> http://www.wnk.at/tmp/i2c/pin_assignment.png
> 
> After downloading the system to the DE2 board i measured the signal levels
> of 
> the SCL and SDA pins on the DE2 board. The SCL pin is at 0V and the SDA
> pin 
> is at 1.2V.
> I'm not sure if this is the expected behavior. In the pin assignment
> editor 
> the pins are set to 3.3V (TTL).
> What I also didn't fully understand yet are the pull-ups. Do I have to add 
> external pull-up resistors (connecting SCL and SDA to 3.3V) or is that 
> somehow done on the board / in the FPGA?
> 
> I'm anything but an digital design / FPGA expert but I have some basic 
> knowledge of VHDL and realted topics. Therefore I'd appreciate any help I
> can 
> get to make this work. In case of success I'd be happy to contribute to
> this 
> project by making the SOPC I2C component available for download.
> 
> Thank you very much,
> -- 
> Thomas Winkler
> tc@t...
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
> 
> 

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