OPENCORES.ORG

Because it was not possible to submit this bug report via tracker,

Looks like a correct fix, although I don't want to speak for Tobias :)
The TG68_fast file has had this corrected already.
I am in the final stages of producing a low cost gaming FPGA board which
will run this core (and the Minimig & my AtariST code), but it also has the
option of fitting a real 68K. I can use this to run the core in lock step
against the real chip much as I did with the T65 and T80 cores, and adjust
the timing if required. I will be making some announcements about my board
in the near future.

MikeJ
www.fpgaarcade.com
----- Original Message ----- 
From: <wzab@i...>
To: <cores@o...>
Sent: Wednesday, January 02, 2008 12:45 PM
Subject: [oc] TG68: problem with simulation in GHDL and synthesis in XST

> Because it was not possible to submit this bug report via tracker,
> I've decided to send it to the forum.4
>
>
> When trying to synthesize TG68 in XST I get the following errors:
>
> ERROR:HDLParsers:812 - "/tmp/fff/test/TG68.vhd" Line 180. A value is
> missing in case.
> ERROR:HDLParsers:812 - "/tmp/fff/test/TG68.vhd" Line 212. A value is
> missing in case.
>
> To fix it I had to add a following clause to the "case" statement:
> (changes in the diff format):
>
> $ diff -c TG68_old.vhd TG68.vhd
> *** TG68_old.vhd 2008-01-02 12:22:10.000000000 +0100
> --- TG68.vhd 2008-01-02 12:21:42.000000000 +0100
> ***************
> *** 179,184 ****
> --- 179,186 ----
>                end if;
>              when "11" =>
>                S_state <= "00";
> +             when others =>
> +               null;
>            end case;
>          end if;
>        end if;
> ***************
> *** 210,215 ****
> --- 212,220 ----
>                           waitm    <= dtack;
>                         end if;
>            when "11" =>
> +             null;
> +           when others =>
> +             null;
>          end case;
>        end if;
>      end if;
>
> Additionally the simulation in the GHDL generates the following error:
> ghdl -a --std=93c --syn-binding -fexplicit --ieee=synopsys TG68.vhd
> TG68.vhd:105:23: actual expression must be globally static
> ghdl: compilation error
>
> This problem is caused by the instantiation of the TG68_fast component
>
>
>  TG68_fast_inst : TG68_fast
>
>    port map (
>
>      clk        => not clk,            -- : in std_logic;
>
>      reset      => reset,              -- : in std_logic;
>
>      clkena_in  => clkena,             -- : in std_logic;
>
> To fix this problem I have created an additional signal:
> signal n_clk std_logic;
> n_clk <= not clk;
>
> and changed the instantiation:
>
>
>  TG68_fast_inst : TG68_fast
>
>    port map (
>
>      clk        => n_clk,            -- : in std_logic;
>
>      reset      => reset,              -- : in std_logic;
>
>      clkena_in  => clkena,             -- : in std_logic;
>
> -- 
> Regards,
> Wojciech M. Zabolotny
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>