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Message
From: Richard Herveille<richard@h...>
Date: Wed Nov 14 11:09:21 CET 2007
Subject: [oc] pseudo random generator verilog code source
There’s an LFSR implementation on opencores as part of the generic_fifos
project.
You may want to check that one out as well.
Richard
_____
From: attachment-0001.htm
> > Date: Thu, 19 Sep 2002 12:14:25 -0700 (PDT)
> > Subject: Re: [oc] pseudo random generator
> > verilog code source
> >
> > >
> > >
> > > I wrote up a webpage about using LSFRs
> > (Linear Shift
> > > Feedback Registers) for pseudo-random
> > number
> > > generation during time off work, maybe it
> > will help:
> > >
> > >
> > attachment-0001.htm
> > l
> > >
> > > A link to an old Altera LFSR core is at
> > the bottom of
> > > the page.
> > >
> > > Hope this helps.
> > >
> > > --- attachment-0001.htm wrote:
> > > > Hi all,
> > > >
> > > > This will generate only one new bit per
> > clock.
> > > > Maybe you need 32 new bits per clock,
> > to send
> > > > over a network ...
> > > >
> > > > A good starting point might be AN49
> > from Altera.
> > > >
> > > > I was unable to find this on the web,
> > so I have
> > > > built my owns,
> > > > starting from there.
> > > >
> > > > Unfortunately, I cannot send the
> > sources
> > > > but I can help you with hints.
> > > >
> > > > Cheers,
> > > > Ovidiu Lupas.
> > > >
> > > >
> > > >
> > > > ----- Original Message -----
> > > > From: Marko Mlinar < attachment-0001.htm >
> > > > To: attachment-0001.htm
> > > > Date: Thu, 19 Sep 2002 10:55:46 +0200
> > > > Subject: Re: [oc] pseudo random
> > generator verilog
> > > > code source
> > > >
> > > > >
> > > > >
> > > > > Here:
> > > > >
> > > > > reg [31:0] poly;
> > > > >
> > > > > always @(posedge clk or posedge
> > reset_poly)
> > > > > if (reset_poly) poly <= #1
> > 32'hdeaddead;
> > > > > else poly <= #1 {poly[30:0],
> > poly[17] ^
> > > > poly[4]};
> > > > >
> > > > > On Thursday 19 September 2002 09:54,
> > Dharmeshbhai
> > > > PATEL wrote:
> > > > > > Hi list,
> > > > > >
> > > > > > Does any one has an idea where i
> > can get the
> > > > verilog code
> > > > > source
> > > > > > for a pseudo random generator
> > (number or signal)
> > > > ?
> > > > > >
> > > > > > Please let me know.
> > > > > >
> > > > > > Thanks in advance.
> > > > > > D.PATEL
> > > > > >
> > > > > >
> > > > > >
> > > >
> > >
> > ___________________________________________
> > __________________
> >
> > > >
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> > > > > "tout compris",
> > > > > > d'un forfait haut débit illimit?
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> > > > ADSL et d'un
> > > > > Modem ADSL simple
> > > > > > ?installer ! Cliquez ici :
> > > > >
> > attachment-0001.htm
> > > > >
> > > >
> > >
> > --
> > To unsubscribe from cores mailing list
> > please visit
> > attachment-0001.htm
> >
> >
>
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