Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: aditya.pandit at iiitb.ac.in<aditya.pandit@i...>
Date: Mon Aug 6 12:40:04 CEST 2007
Subject: [oc] AC97 Controller
Sir,

I am doing a project with spartan3 FPGA and is in a process interfacing
the essential peripherals like AC 97,VGA etc with it. I intend to keep it
opensource and hence i am using Wishbone.
I would like to know how to simulate this core in ISE or
Modelsim. The simulation requires either .tcl or .xco file. Please suggest
a method to run these verilog codes.

Thanks & Regards
Aditya Pandit

----- Original Message -----
From: Rudolf Usselmann <rudi@a...>
To: OPENCORES <cores@o...>
Date: Sat, 05 May 2001 08:39:42 +0700
Subject: [oc] AC97 Controller

>
>
>
> I have added a new project: WISHBONE AC97 Controller
>
> This an Audio Codec Controller compliant to the AC97
> specification (Rev. 2.2) from Intel.
>
> Please take a look !
>
> Cheers !
> --
> rudi
>