OPENCORES.ORG

However, I do not see this happening for the ASIC tool vendors, who make

The EDIF standard is available for download from IEEE for $9.
I am sure there are IEEE members/fellows on this list that can assist in
obtaining the standard as a contribution to open source tools.

You can also take a look at the OADB. If I am not mistaken it has an EDIF
reader, plus verilog, vhdl, and DEF readers.
That would be a good starting point for an open source tool.

Richard

-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Attila Kinali
Sent: Wednesday, August 01, 2007 10:02 AM
To: Discussion list about free open source IP cores
Subject: Re: [oc] future of open source fpga design tools

On Tue, 31 Jul 2007 19:01:08 +0100
Shawn Tan <shawn.tan@a...> wrote:

> However, I do not see this happening for the ASIC tool vendors, who make
money 
> on the secret sauces they put inside their software. I'd settle for
industry 
> wide standard file formats. This would allow designers to mix + match tool

> chains with design libraries and fab processes.

Apropos standard file formats, i've been looking for documentation
on the EDIF standard(s)for quite some time now but couldn't find anything
usable. Yes, i could buy the standards, but 400CHF is kind of expensive
just to have a look and decide whether it's worth to invest time and
energy into doing some OSS tools around EDIF.

Does anyone know any good sources for EDIF?

Thanks in advance

				Attila Kinali
-- 
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
                         -- Deed of Morred
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