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Message
From: Günter Dannoritzer<dannoritzer@w...>
Date: Fri Jul 27 10:45:31 CEST 2007
Subject: [oc] Help with choosing a FPGA
a2e@i... wrote:
[...]
>
> My ultimate goal is to capture data from a CMOS image sensor and store
> it to a hard drive. The CMOS sensor itself will either be clock out
> data at a frequency of 48Mhz or 96Mhz. My first question is how can I
> tell if a particular FPGA is capable of reading in data at these
> rates? I have looked over various datasheets but I have to admit I
> have not been able to find a straight answer.
This problem is actually twofold.
One thing you need to figure out is what clock rate you need to
interface the CMOS sensor and then look in the FPGA data sheet whether
the I/O pins support those timing constraints.
The second thing to consider is the maximum frequency you can run your
design in an FPGA. This one depends on the logic. Generally speaking,
the more complex the design is, the lower gets the maximum speed you can
run it with. But then there is still the possibility to speed up designs
by the way they are designed. So the same function, carefully designed
can achieve better maximum frequencies than if it were sloppy designed.
At the end, the synthesis tool will tell you what maximum clock you can
achieve with your design.
In the data sheet you will only find what maximum external clock you can
apply to your FPGA. But that is not necessarily the clock you are using
inside for the logic. FPGAs have so called clock manager functions. They
allow to step up or down the external applied clock.
In the Xilinx FPGAs this is called the Digital Clock Manager (DCM). In
the data sheet you will find what maximum input clock the DCM allows.
See for example table 70 in the data sheet.
http://direct.xilinx.com/bvdocs/publications/ds312.pdf
The data sheet will also tell you how much the DCM can bring this clock up.
>
> The two devboards I am looking at are the “Spartan 3E Starter Board”
> from Dililent or the “Cyclone II FPGA Starter Development Kit” from
> Altrea. Would either of these boards be capable of doing what I need?
>
> As for cores I am thinking that I will need to run the following:
>
> OpenRISC 1200
> General-Purpose I/O (GPIO) Core
> I2C controller core
> tri-mode Ethernet MAC
> VGA/LCD Controller
> OCIDEC (OpenCores IDE Controller)
Look into the documentation of the specific cores whether they provide
synthesis information for a specific FPGA. This will give you an idea
how much of the FPGA the respective core will use and what clock rate
you can use.
Hope that helps.
Cheers,
Guenter
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