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Message
From: ameliaw.azman at gmail.com<ameliaw.azman@g...>
Date: Tue Jul 24 18:09:28 CEST 2007
Subject: [oc] Please advise me on my VHDL study
Hi Felipe,It's important to realise that there are VHDL syntax that cannot be
synthesized. I would suggest a book by Andrew Rushton "VHDL for logic
synthesis" second version.
Cheers!
----- Original Message -----
From: Felipe Uderman<felipe.uderman@g...>
To:
Date: Mon Jul 23 15:32:08 CEST 2007
Subject: [oc] Please advise me on my VHDL study
> Hello,
>
> I am starting to program with VHDL. I am following the book Circuit
> Design
> with VHDL by Volnei A. Pedroni. I am also using ModelSim for my
> simulations,
> and still learning how to use this tool.
> I found opencores.org very good, as it provides free and open
> source VHDL
> code. This is very use for the ones that are learning and also for
> the ones
> that allready work with complex VHDL projects.
> I would like to hear from you some coments about my choices for the
> book and
> the tool, and also some other bibliography sugestions. I also would
> like to
> hear some coments on how to best use the opencores resources to
> learn and
> work with VHDL.
> Thank you,
> Felipe
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