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From: Andreas<x-opencores.org@a...>
Date: Mon Jul 16 18:03:15 CEST 2007
Subject: [oc] Problem with T51 core & Xilinx ISE
Thanks for all the replies. The reason was the ROM. ISE didn't manage
to infer a block RAM from the select-case-structure. I changed it to a
array, now everything is OK.

Andreas

----- Original Message -----
From: Guy Hutchison<ghutchis@g...>
To:
Date: Mon Jun 25 20:35:29 CEST 2007
Subject: [oc] Problem with T51 core & Xilinx ISE

> Hi Andreas,
>
> Doesn't sound normal. I used to run synthesis of the TV80 core
> (similar
> size) + DUT into a Virtex-4 device, and synthesis was on the order
> of 5
> minutes. Going from a new netlist to a BIT file took less than an
> hour.
> It will probably use distributed RAM because register files and
> various
> other parts are async read. The TV80 uses relatively small amounts
> of it,
> but the T51 may have significantly more.
> The only non-standard thing I did was to run the whole process from
> the
> command line.
> - Guy
> On 6/25/07, attachment-0001.html
>
>