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From: zhangjiyong at fiberhome.com.cn<zhangjiyong@f...>
Date: Mon Jul 9 13:57:15 CEST 2007
Subject: [oc] Memory controller, Ahb/apb bridge

----- Original Message -----
From: Richard Herveille <richard@a...>
To: cores@o...
Date: Wed, 24 Apr 2002 10:03:42 +0700
Subject: Re: [oc] Memory controller, Ahb/apb bridge

>
>
>
>
> Do you want to make this an OpenSource project, and share it on
> OpenCores ??
> If so, OpenCores uses the Wishbone Bus for it's cores.
> Converting the Wishbone Bus to the AMBA bus should be
> straightforward.
>
> For models, documentation etc. check the OpenCores memory
> controller.
>
> Richard
>
>
> >Hi list,
> >
> >I would like to make an multiport memory controller interface
> >which interface with AMBA AHB bus. If anyone have some model
> >I'm interested by (Documentation,verilog vhdl source
> code,testbench..)
> >
> >For example Memory controller from ARM Primcell.
> >
> >I also want to make ahb/apb bridger. If Any one have somethins
> about
> >I'm also interested by(design spec,Code source VHDL,Verilog)
> >
> >thaks in advance.
>