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Message
From: vax11780 at porky.vax-11.org<vax11780@p...>
Date: Tue Jul 3 16:24:01 CEST 2007
Subject: [oc] Xilinx ISE error when using DDR SDRAM cores on Spartan-3 5000
On Tue, 3 Jul 2007, yasirmm@g... wrote:> Hi guys,
>
> I have been trying to implement DDR SDRAM controller core for an FPGA
> board with 1GB SODIMM DDR SDRAM. I have tried the cores from
> opencores.org and also the Xilinx MIG 1.6 (with a modified UCF) but
> both cores would gave me the following error:
>
> ERROR:Place:17 - The placement constraints of the IOBs dqs_q<1> and
> data<7> makes this design unroutable due to a physical routing
> limitation. This device has a shared routing resource connecting the
> ICLK and OTCLK pins on pairs of IOBs. This restriction means that
> these pairs of pins must be driven by the same signal or one of the
> signals will be unroutable. Before continuing please remove the
> placement constraints or move one of these IOBs to a new location.
>
> Any help/suggestion will be greatly appreciated.
>
> Thank you very much!
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
You are attempting to use more resources (IE clock wires) from the core to
the IO ring. The easiest solution is to unconstrain the pins and allow the
router to automatically place them. You may have to unconstrain more than
just the ones reported to free up resources to get a place-able design.
Clint
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