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From: Miha Dolenc<mihad@o...>
Date: Tue Jul 3 09:23:22 CEST 2007
Subject: [oc] Xilinx ISE error when using DDR SDRAM cores on Spartan-3 5000
Hi!

This happens when two adjacent IOB pairs use different input
or output clocks.
(A pair of IOB blocks shares one clock net for input flip-flops
and one clock net for output and output enable flip-flops).
If any of these conflicting signals is a single data rate signal,
you can pull it out of IOB using the UCF file.

Regards,
Miha Dolenc

----- Original Message -----
From: <yasirmm@g...>
To: <cores@o...>
Sent: Tuesday, July 03, 2007 6:03 AM
Subject: [oc] Xilinx ISE error when using DDR SDRAM cores on Spartan-3 5000


> Hi guys,
>
> I have been trying to implement DDR SDRAM controller core for an FPGA
> board with 1GB SODIMM DDR SDRAM. I have tried the cores from
> opencores.org and also the Xilinx MIG 1.6 (with a modified UCF) but
> both cores would gave me the following error:
>
> ERROR:Place:17 - The placement constraints of the IOBs dqs_q<1> and
> data<7> makes this design unroutable due to a physical routing
> limitation. This device has a shared routing resource connecting the
> ICLK and OTCLK pins on pairs of IOBs. This restriction means that
> these pairs of pins must be driven by the same signal or one of the
> signals will be unroutable. Before continuing please remove the
> placement constraints or move one of these IOBs to a new location.
>
> Any help/suggestion will be greatly appreciated.
>
> Thank you very much!
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores

Reference	Author
[oc] Xilinx ISE error when using DDR SDRAM cores on Spartan-3 5000	Yasirmm