Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: yasirmm at gmail.com<yasirmm@g...>
Date: Tue Jul 3 06:03:54 CEST 2007
Subject: [oc] Xilinx ISE error when using DDR SDRAM cores on Spartan-3 5000
Hi guys,

I have been trying to implement DDR SDRAM controller core for an FPGA
board with 1GB SODIMM DDR SDRAM. I have tried the cores from
opencores.org and also the Xilinx MIG 1.6 (with a modified UCF) but
both cores would gave me the following error:

ERROR:Place:17 - The placement constraints of the IOBs dqs_q<1> and
data<7> makes this design unroutable due to a physical routing
limitation. This device has a shared routing resource connecting the
ICLK and OTCLK pins on pairs of IOBs. This restriction means that
these pairs of pins must be driven by the same signal or one of the
signals will be unroutable. Before continuing please remove the
placement constraints or move one of these IOBs to a new location.

Any help/suggestion will be greatly appreciated.

Thank you very much!

Follow up	Author
[oc] Xilinx ISE error when using DDR SDRAM cores on Spartan-3 5000	Miha Dolenc