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From: Mark McDougall<markm@v...>
Date: Mon Jul 2 07:58:25 CEST 2007
Subject: [oc] WISHBONE signals question
darus@m... wrote:

> So, at the rising edge 1 master sees ACK from slave and latches data.
> But before the same edge, master should present new address on ADR_O!
> But how master knows in advance, that slave will assert ACK on edge 1?

Umm, no, the new address is asserted in logic clocked on clock edge 1, so
it will appear _after_ that clock edge - as in figure 3-6!

The master is only going to present a new address if it samples ACK_I on
that clock edge.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266