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Message
From: Daniel Lenski<dlenski@g...>
Date: Mon Jul 2 06:58:55 CEST 2007
Subject: [oc] has anyone got uCore to work?
Hi all,
I've been experimenting with the two Verilog MIPS cores on
OpenCores.org. YACC is a pretty simple core and works fine for me,
but I'm more interested in the uCore implementation which looks like
it'll be higher-performing and has more features.
I have got the uCore test bench (ucsys-0.0.1/src/ucore/tb/ucore_tb.v)
to compile fine with Icarus Verilog version 0.8 or the latest CVS
snapshot... and the simulator will run and decode instructions, but
not execute them properly. It messes up all the registers and the
pipeline stages seem to take almost random amounts of time.
The original author gave a snapshot of the simulator logs of proper
operation (ucsys-0.0.1/sim/) directory, so it seems like it should
work under _some_ simulators at least...
Has anybody got it to work, and could give me some pointers? Thanks!
Dan
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