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Message
From: des00 at opencores.org<des00@o...>
Date: Thu May 24 17:06:09 CEST 2007
Subject: [oc] Question on Ethernet MAC 10/100 Mbps
Hi everybody! Could you explain: how this MAC will be processed Pause frames in a
mode r_PassAll = 0?
In eth_maccontrol i found follow condition
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
(~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <=#Tp (~RxError);
else
RxB_IRQ <=#Tp 1'b0;
end
As I understand in a mode r_PassAll = 0 signal RxB_IRQ should not be
exposed, but ReceivedPauseFrm is not Level signal in r_PassAll = 0
mode. Becouse in eth_recivercontorl there is
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ReceivedPauseFrm <=#Tp 1'b0;
else
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm &
(~r_PassAll))
ReceivedPauseFrm <=#Tp 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
ReceivedPauseFrm <=#Tp 1'b1;
end
ReceivedPauseFrm is 1 cycle pulse signal in mode r_PassAll = 0 and
cannot be registred in
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun,
InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame,
LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <=#Tp RxStatusIn;
end
becouse LoadRxStatus is valid at the end of frame recive process.
As i understant at reception of a PAUSE frame RxB_IRQ interrupt will
be exposed! But that is not correct!
Could somebody help me please ? :)
Denis
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